應用新式球面解碼演算法可重置式軟性輸出多輸入多輸出偵測器之晶片設計

Abstract

本論文提出一高天線數、軟性輸出、可重置式多輸入多輸出偵測器之晶片設計。此多輸入多輸出偵測器晶片具有多項重要的特色(Key feature)： 1.採用新式高效能球面解碼演算法 2.支援8x8 64QAM高天線數高調變系統 3.支援軟性輸出(Soft-output)以及迭代候選人列表(Candidate list)輸出 4.可重置式設計，支援多種天線數及調變數系統，共21種模式 相較於其他已發表晶片，功率消耗最低 在演算法階段，本論文採用”改良式 最佳優先搭配快速向下搜尋(Modified best-first with fast decent, MBF-FD)演算法”，大幅提升球面解碼器之搜尋效能。在硬體設計方面，本論文針對新式演算法提出多項新式硬體架構，如”管線式四元雙堆積架構(Pipelined quad-deap)”等大幅增加硬體效能。並採用許多電路設計技巧，如華倫斯數(Wallace tree)、布斯編碼(Booth Encoding)、閘式時脈(Gated clock)來達到低功率、高速、低複雜度的晶片設計。 本晶片是目前已發表的多輸入多輸出偵測器晶片中，唯一可以支援8x8 64QAM高天線數高調變系統之晶片。本晶片相容於軟性輸入錯誤更正碼(Soft-input error correcting codes)及迭代式解碼架構(Iterative decoding)，並能支援2x2, 3x3, …8x8所有天線，QPSK, 16QAM, 64QAM等所有調變組合。本晶片透過國家晶片中心，已於CIC T13L-97B梯次下線，並實際利用國家晶片中心機台量測，晶片最高操作時脈可達198MHz，輸出率可達296.6Mbps。跟其他已發表之MIMO球面解碼晶片相比較，本晶片之消耗功率也最低，效能相當優異。

In this work, VLSI implementation of a configurable, soft-output MIMO detector is presented. The proposed IC can support up to 8×8 64QAM spatial multiplexing MIMO communications, which surpasses all reported MIMO detector ICs in antenna number and modulation order. Moreover, this chip provides configurable antenna number from 2×2 up to 8×8 and modulation order from QPSK to 64QAM. Its outputs include bit-wise log likelihood ratios (LLRs) and a candidate list, making it compatible with powerful soft-input decoders and iterative decoders. The MIMO detector adopts a novel sphere decoding algorithm with high decoding efficiency and better error rate performance, called modified best first with fast descent (MBF-FD). Moreover, a low-power pipelined quad-DEAP circuit for efficient node pool management and several circuit techniques are implemented in this chip. When this IC is configured as 4×4 64 QAM and 8×8 64QAM soft-output MIMO detectors, it achieves average throughputs of 297Mbps and 207.1Mbps with only 58.2mW and 74.8mW respective power consumption and negligible performance degradation (less than 0.1dB in SNR).