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標題: | 考慮光罩效應之積體電路擺置規劃系統 Lithography Friendly Multilevel Analytical Placement |
作者: | Wen-Chi Chao 趙文綺 |
指導教授: | 張耀文(Yao-Wen Chang) |
關鍵字: | 置放,微影,多層次,解析式,光學鄰近校正技術,可製造性, placemet,lithography,multilevel,analytical,OPC,manufacturability, |
出版年 : | 2009 |
學位: | 碩士 |
摘要: | 由於次波長微影技術, 製成需要仰賴密集地使用解析度增強技術
(Resolution-Enhancement Techniques, RETs),其中光學鄰近校正技術 (Optical Proximity Correction, OPC) 最常被工業界用來增強可製造性。此外, 考慮可製造性的實體設計更成為設計流程中輔助增強可製造性的主流。 在本篇論文中,我們提出了第一個考慮光學鄰近校正技術下幫助微影的多層 次解析式置放。我們先根據光學鄰近校正技術後的微影模擬結果,建立一個元件 對元件造成的微影代價計算模型,接著利用這個模型來引導置放。根據多層次解 析式的置放架構,我們提出了兩個估計微影代價的方法來引導初期置放,接著在 合法化階段中考慮微影代價,最後在細部置放階段同時最佳化微影代價和線長。 我們利用ISCAS[2] 和ISPD04[1] 電路來做測試。光是靠我們的細部置放 演算法,就可以讓兩組測試電路分別降低平均12.73% 和 36.86% 的微影代價。 相較於先前所提出的演算法中效果最好的多列最佳化演算法[12],我們所提出 的演算法更進一步增進了11.08% 和 34.01% 的可製造性。為了觀察每個階段的 功效,我們引用了不同的流程來做驗證。而從實驗結果我們可以看出各個階段對 於彼此有正面的影響。相較於只考慮線長的NTUplace3[6],完整的幫助微影置 放可以分別對ISCAS 和ISPD04 測試電路減少26.98% 和50.94% 的微影代價,並且只增加不到3% 的線長。這個結果顯示我們的作法可以在幾乎相同的線長品質 下顯著的增進可製造性,並且達到比所有先前演算法所得到的結果都要好的效 果。 Due to the sub-wavelength lithography, manufacturing requires intensive use of Resolution-Enhancement Techniques (RETs), among which Optical Proximity Cor- rection (OPC) is the most popular technique in industry, to improve printability. Moreover, physical design for manufacturability becomes the major trend in the design flow to assist the success of manufacturing. In this thesis, we propose the first lithography friendly multilevel analyt- ical placement considering OPC. We first generate a cell-to-cell lithography cost model based on post-OPC lithography simulation, and then use this model to guide our placement. Based on the multilevel analytical placement framework, we use a probability-based cost estimation model for the clustering process, and a ratio- based cost estimation model for the spreading process, to estimate lithography cost. The clustering and spreading processes are adjusted by our cost estimation models. With the information provided by our model, our global placement is able to gen- erate a low lithography cost result for the next stage. Then legalization aligns cells to nearby rows considering lithography cost. Finally, detailed placement simultane- ously optimizes lithography cost and wirelength. We test our approach on ISCAS benchmark circuits [2] and ISPD04 IBM benchmark circuits [1]. Based on the experimental results, our lithography friendly detailed placement alone can already achieve 15.06% and 36.86% lithography cost reduction. The results are 13.94% and 34.01% better on printability than the pre- viously proposed detailed placement algorithm-Multiple-Row Optimization Algo- rithm [12], which is the most effective algorithm in the literature. To examine the effectiveness of our approach, we apply different placement flows and compare the results with the un-lithography-aware wirelength-driven NTUplace3 [6]. The effec- tiveness of each stage and the positive impacts between different stages are observed from the results. By applying the complete flow (which has the highest quality on printability) of our lithography friendly placement, we can achieves 20.86% and 50.94% lithography cost reduction on ISCAS benchmark circuits [2] and ISPD04 IBM benchmark circuits [1], respectively, comparing with wirelength-driven NTU- place3, with only less than 3% wirelength overhead. The results show that our approach can effectively achieve significant improvements on printability, which has the best results among all the related works, without notable wirelength quality decrease. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/44162 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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