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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Chang-Yi Liu | en |
dc.contributor.author | 劉昶毅 | zh_TW |
dc.date.accessioned | 2021-05-14T17:42:05Z | - |
dc.date.available | 2020-08-21 | |
dc.date.available | 2021-05-14T17:42:05Z | - |
dc.date.copyright | 2015-08-21 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-08-19 | |
dc.identifier.citation | [1] HomePlug Alliance official website: http://www.homeplug.org/
[2] “HomePlug AV white paper,” HomePlug Powerline Alliance, 2005. [3] 劉邦楷, “A Line Driver Design for Powerline Communication Systems,” Master Thesis, NTU, 2012. [4] K. N. Leung, P. K. T. Mok, W. H. Ki, and J. K. O. Sin, “Three-stage large capacitive load amplifier with damping-factor-control frequency compensation,” IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 221-230, Feb. 2000. [5] K. N. Leung and P. K. T. Mok, “Analysis of multistage amplifier-frequency compensation,” IEEE Trans. Circuits Syst. I, vol. 48, no. 9, pp. 1041-1056, Sept. 2001. [6] K. N. Leung and P. K. T. Mok, “Nested Miller compensation in low-power CMOS design,” IEEE Trans. Circuits Syst. II, vol. 48, no. 4, pp. 388-394, April 2001. [7] 詹凱翔, “A High Dynamic Range, Low Gain Error Programmable Gain Amplifier for Powerline Communication System,” Master Thesis, NTU, 2012. [8] Spectrum Planning Team, Radiofrequency Planning Group, Australian Communications Authority, Broadband Powerline Communications Systems: A Background Brief, Sep. 2003. Retrieved from: https://docs.google.com/viewer?url=http://www.acma.gov.au/webwr/radcomm/frequency_planning/spps/0311spp.pdf&pli=1 [9] Halid Hrasnica, Abdelfatteh Haidine, and Ralf Lehnert, Broadband Powerline Communications Networks: Network Design, England, John Wiley & Sons Ltd, 2004. [10] HomePlug. (n.d.). Retrieved March 19, 2012, from http://en.wikipedia.org/wiki/HomePlug [11] Olivier Monnier, “TI Delivers Flexible Power Line communications Solutions,” White Paper, Texas Instruments, 2010. [12] “HomePlug AV specification version 1.1,” HomePlug Powerline Alliance, May 2007. [13] N. Weling, “Expedient permanent PSD reduction table as mitigation method to protect radio services,” IEEE International Symposium on Power Line Communications and Its Applications (ISPLC), pp. 305-310, April 2011. [14] K. Findlater, T. Bailey, A. Bofill, N. Calder, S. Danesh, R. Henderson, W. Holland, J. Hurwitz, S. Maughan, A. Sutherland, and E. Watt, “A 90nm CMOS dual-channel powerline communication AFE for Homeplug AV with a Gb extension,” IEEE ISSCC Dig. Tech. Papers, pp. 464-628, Feb. 2008. [15] M. Tlich, R. Razafferson, G. Avril, and A. Zeddam, “Outline about the EMC properties and throughputs of the PLC systems up to 100 MHz,” IEEE International Symposium on Power Line Communications and Its Applications (ISPLC), pp. 259-262, April 2008 [16] R. Schaumann, M. E. V. Valkenburg, and H. Xiao, Analog Filter Design, 2nd edition Oxford University Press, 2011 [17] A. N. Mohieldin, E. Sanchez-Sinencio, and J. Silva-Martinez, “A fully balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector,” IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 663-668, April 2003. [18] C. Lujan-Martinez, R. G. Carvajal, J. Galan, A. Torralba, J. Ramirez-Angulo, and A. Lopez-Martin, “A tunable pseudo-differential OTA with -78 dB THD consuming 1.25 mW,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 6, pp. 527-531, June 2008. [19] M. S. Kappes, “A 3-V CMOS low-distortion class AB line driver suitable for HDSL applications,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 371-376, March 2000. [20] V. Dhanasekaran, J. Silva-Martinez, and E. Sanchez-Sinencio, “Design of three-stage class-AB 16 Ω headphone driver capable of handling wide range of load capacitance, ” IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1734-1744, June 2009. [21] D. M. Monticelli, “A quad CMOS single-supply op amp with rail-to-rail output swing,” IEEE J. Solid-State Circuits, vol. SC-21, no. 6, pp. 1026-1034, Dec. 1986. [22] Xicheng Jiang, Jungwoo Song, T. L. Brooks, Jianlong Chen, V. Chandrasekar, F. Cheung, S. Galal, D. Cheung, G. C. Ahn and M. Bonu, “A 10mW stereo audio CODEC in 0.13μm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 82-83, Feb. 2010. [23] G. Cesura, A. Bosi, F. Rezzi, R. Castello, Jenkin Chan, SaiBun Wong, Chi Fan Yung, O. Carnu, and T. Cho, “A VDSL2 CPE AFE in 0.15μm CMOS with integrated line driver,” IEEE ISSCC Dig. Tech. Papers, pp. 108-109,109a, Feb. 2009. [24] M. S. Kappes, “A 3-V CMOS low-distortion class AB line driver suitable for HDSL applications,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 371-376, March 2000. [25] E. Seevinck, and R. J. Wiegerink, “Generalized translinear circuit principle,” IEEE J. Solid-State Circuits, vol. 26, no. 8, pp. 1098-1102, Aug. 1991. [26] B. A. Minch, “MOS translinear principle for all inversion levels,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 2, pp. 121-125, Feb. 2008. [27] P. K. Liu, S. Y. Hung, C. Y. Liu, M. H. Hsieh, and C. C. P. Chen, “A 52 dBc MTPR line driver for powerline communication HomePlug AV standard in 0.18-μm CMOS technology,” in Proc. IEEE Int. Symp. Circuits Systems, May. 2013, pp. 1404–1407. [28] B. Hernes and W. Sansen, “Distortion in single-, two- and three-stage amplifiers,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 52, no. 5, pp. 846–856, May 2005. [29] G. Palumbo and S. Pennisi, “Harmonic distortion in three-stage nested-Miller-compensated amplifiers,” in Proc. IEEE Int. Symp. Circuits Systems, May. 2004, pp. 485–488. [30] S. O. Cannizzaro, G. Palumbo, and S. Pennisi, “Distortion analysis of Miller-compensated three-stage amplifiers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 5, pp. 961–976, May 2006. [31] F. Resta1, M. De Matteis1, A. Pezzotta1, S. D’Amico2, and A. Baschirotto, “A 30MHz 28dBm-IIP3 3.2mW Fully-Differential Sallen-Key 4th-Order Filter with Out-of-Band Zeros Cancellation,” in Proc. IEEE Int. New Circuits Syst. Conf., Jun. 2015. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/4404 | - |
dc.description.abstract | 為了家庭數位化的願景,具有高速傳輸速率的家庭網路將會不可或缺。為了達到這個目標,利用電力線作為傳輸媒介的電力線通訊是一解決方法。此種通訊的最大好處是可以直接利用串連起電器的電線作傳輸,可以省卻再拉線的成本。為了達到高傳輸量,再傳輸協定上把原本通訊頻寬從2-28MHz拓展到2-86MHz。
但電力線的特徵阻值變化極大且與頻率並無相關,這會使得在設計電力線驅動器上會造成問題發生,故在此設計上會以平均阻值作為設計考量。由於使用CMOS 90奈米製程,由於無高電壓供使用,在此利用一升壓變壓器當作介面來把訊號載到電力線上,但卻會使得驅動器的負載更小,這亦會增加困難。 在驅動器穩定性考量上,在多級驅動電路中會以巢狀式米勒補償來穩定並會以阻尼因子控制網絡來抑制開迴路頻率響應產生的高頻凸起,並在電阻性負載改變時候的高頻凸起亦能被抑制。另外在中間電路中會再加入一前饋路徑來改善因輸出級尺寸大而有較大的寄生電容所造成的頻寬不足。 在系統量測上,數位類比轉換電路和傳輸器類比前端包含濾波器和驅動電路的輸出線性度量測上分別在HomePlug AV和HomePlug AV2中有達到大於40dB和36dB的結果。 | zh_TW |
dc.description.abstract | The high speed communication network in home is indispensable to achieve the vision of digital home. In order to achieve the goal, transmitting data through power line is adopted since it saves the cost of extra cable setting. Moreover, to improve the data rate, the signal bandwidth is increased from the 2-28MHz for Home Plug AV specification to the 2-86MHz for Home Plug AV2 specification in this topic.
The characteristic of power line is different everywhere in the world. Moreover, the output loading existing in the line driver output is in huge variation due to the channel response. An average value of equivalent resistance for power line is considered in design. For line driver linearity issue, three stage amplifier and feed-forward compensation are used to achieve high loop gain. Damping factor control network and nested Miller compensation technique are used to suppress the open-loop frequency peak and improve stability. As a result, the peaking is suppressed even when the output resistive loading changes. The transmitter amplifier of transmitter analog front end in power line communication is realized in TSMC 90nm CMOS process. Moreover, the supply voltage is 2.5V for I/O usage. Multi-tone power ratio (MTPR) is one of targets in linearity testing. The MTPR measurement result of the output for transmitter is higher than 40 dBc in HomePlug AV and 36dBc for HomePlug AV2. The recovered QAM in HomePlug AV is 256 QAM and 64 QAM for HomePlug AV2 application. | en |
dc.description.provenance | Made available in DSpace on 2021-05-14T17:42:05Z (GMT). No. of bitstreams: 1 ntu-104-R98943039-1.pdf: 3586626 bytes, checksum: c70e235c0cbc37a0eb6912728ef6ea7c (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | 口試委員會審定書 i
致謝 ii 中文摘要 iii Abstract iv LIST OF FIGURES ix LIST OF TABLES xii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Power Line Communication 4 2.1 Broadband Power Line Communication 5 2.2 HomePlug 5 2.2.1 Usage 6 2.2.2 Version of HomePlug Standard 7 2.3 Analog Front end of PLC System 9 2.3.1 In-House Applications 9 2.3.2 The Challenge of Power Line Communications 11 2.4 Design Consideration 12 2.4.1 Power Line Channel Response 12 2.4.2 EMC Characteristic and Signal Spectrum 14 2.4.3 Line Driver Design Consideration 15 Chapter 3 Analog Front End of Transmitter in PLC System 17 3.1 Introduction 17 3.2 Sallen-Key Low Pass Filter 17 3.3 PLC Line Driver 21 3.3.1 Closed-Loop Line Driver 21 3.3.2 Half Circuit of Proposed Pseudo-Differential Operational Amplifier 22 3.3.3 Damping Factor Control Network 25 3.3.4 Distortion Consideration in NMC Amplifier 28 3.3.5 Open-Loop AC Simulation 31 3.3.6 Closed-Loop AC Simulation 32 3.3.7 Transient Simulation Result of Closed-Loop Line Driver 34 3.4 Transmitter Simulation 37 Chapter 4 Transmitter Measurement 38 4.1 PLC Chip Photo and Transmitter Amplifier Layout 38 4.2 Measurement Environment Setting 39 4.3 MTPR and Recovered QAM Measurement 41 4.3.1 HomePlug AV Specification Measurement 41 4.3.2 HomePlug AV2 Specification Measurement 43 4.3.3 Performance Summary 45 Chapter 5 Conclusion 46 References 47 | |
dc.language.iso | en | |
dc.title | 應用於電力線通訊之寬頻傳輸端放大器設計 | zh_TW |
dc.title | A Wideband Transmitter Amplifier Design for Power Line Communication Application | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 曹恆偉(Hen-Wai Tsao),黃俊朗(Jiun-Lang Huang) | |
dc.subject.keyword | 電力線通訊,傳輸器類比前端,線驅動器,阻尼因子控制網絡,巢狀式米勒補償, | zh_TW |
dc.subject.keyword | power line communication,transmitter analog front end,line driver,damping factor control network,nested Miller compensation, | en |
dc.relation.page | 51 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2015-08-19 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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