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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 盧信嘉 | |
dc.contributor.author | Chun Pan | en |
dc.contributor.author | 潘俊 | zh_TW |
dc.date.accessioned | 2021-06-15T02:31:16Z | - |
dc.date.available | 2010-08-18 | |
dc.date.copyright | 2009-08-18 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-08-14 | |
dc.identifier.citation | [1] International Technology Roadmap for Semiconductors 2007 Edition Assembly and
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Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Shen, and Clair Webb, “Die stacking (3D) microarchitecture,” 39th Annual IEEE/ACM International Symposium on Microarchitecture, December 2006, pp. 469-479. [7] James A. Burns, Brian F. Aull, Chenson K. Chen, Chang-Lee Chen, Craig L. Keast, Jeffrey M. Knecht, Vyshnavi Suntharalingam, Keith Warner, Peter W.Wyatt, and Donna-Ruth W. Yost, “A wafer-scale 3-D circuit integration technology,” IEEE Transactions on Electron Devices, Vol. 53, Issue 10, pp. 2507-2516. October 2006. 79 [8] S. Denda, “Process examination of through silicon via technologies,” International Conference on Polymers and Adhesives in Microlelctronics and Photonics, January 2007, pp. 149-152. [9] Kouichi Kanda, Danardono Dwi Antono, Koichi Ishida, Hiroshi Kawaguchi, Tadahiro Kuroda, and Takayasu Sakurai, “1.27 Gb/s/pin 3mW/pin wireless superconnect (WSC) Interface Scheme,” 2003 IEEE International Solid-State Circuits Conference, February 2003, pp. 186-187. [10] Mamoru Sasaki, and Atsushi Iwata, “A 0.95mW/1.0Gbps spiral-inductor based wireless chip-interconnect with Asynchronous Communication Scheme.” 2005 Symposium on VLSI Circuits, June 2005, pp. 348-351. [11] David K. Cheng, Fundamentals of Engineering Electromagnetics, New Jersey: Prentice-Hall, 1993 [12] David K. Cheng, Field and wave electromagnetic, 2nd Edition, New York: Addison Wesley, 1989. [13] Roger E. Ziemer and William H. Tranter, Principle of Communications, 5th Edition, New York: John Wiley & Sons, 2002. [14] Behzad Razavi, RF Microelectronics, New Jersey: Prentice-Hall, 1998. [15] Behzad Razavi, Design of Integrated Circuits for Optical Communications, New York: McGraw Hill, 2003. [16] Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, and Tadahiro Kuroda, “Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect,” IEEE Journal of Solid State Circuits, Vol. 40, Issue 4, pp. 829-837, April 2005. [17] Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, and Tadahiro Kuroda, “A 1Tb/s 3W inductive-coupling transceiver for 3D-stack inter-chip clock and data link,” IEEE Journal of Solid State Circuits, Vol. 42, Issue 1, pp. 111-122, January 2007. 80 [18] Chien-Wei Huang, Differential Bandpass Filters for WLAN and Antenna Switch Module for GPRS Applications Using LTCC Process, Graduate Institute of Electronics Engineering, National Taiwan University Master Thesis. July 2006. [19] Guan-Ming Wu “Wireless inter-chip signal interconnect using vertical coupled inductors for 3D-IC applications”, Graduate Institute of Electronics Engineering, National Taiwan University Master Thesis. July 2008. [20] Xu Jian, J, Wilson, S, Mick, Luo Lei, and Franzon, “2.8Gb/s inductively coupled interconnect for 3-D ICs”. 2005 Symposium on VLSI Circuits, June 2005, pp.352 – 355. [21] David M. Pozar, Microwave Engineering, 3rd Edition, New Jersey: John Wiley & Sons, 2005. [22] Hsin-Chia Lu, Tzu-Wei Chao, Tuck-Boon Chan and Yien-Tien Chou, “LTCC layer-to-layer mis-alignment resistant coupled inductor and bandpass filter,” 2009 IEEE MTT-S International Microwave Symposium (IMS), Boston, U.S.A., June 2009, pp.1613-1616. [23] Alfonso Carlosena, and Antonio Manuel-Lazaro, “A novel design method for phase-locked loops of any order and type,” IEEE International Midwest Symposium on Circuits and Systems, August 2006, pp. 569-573. [24] National Semiconductor Application Note 1001, July 2001. [25] Suhas Kulhalli, Sumantra Seth, and Shih-Tsang Fu, “An integrated linear RF power detector,” International Symposium on Circuits and Systems, Vol. 1, May 2004, pp. 625-628. [26] Andy Kuo, Touraj Farahmand, Nelson Ou, Sassan Tabatabaei, and Andre Ivanov, “Jitter models and measurement methods for high-speed serial interconnects,” 2004 International Test Conference, October 2004, pp. 1295-1302. [27] Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio Lombardi, and Minsu Choi, “Analysis and simulation of jitter for high speed channels in VLSI systems,” 2007 IEEE Instrumentation and Measurement Technology Conference, May 2007, pp. 1-4. 81 [28] Gene L. Harding, “A Jitter Education: A more detailed look at jitter for the sophomore,” Frontiers in Education Conference, Annual, October 2007, pp. T1C-17-T1C-21. [29] Wavecrest Corporation, Technical Resource, “Understanding Jitter.” http://www.wavecrest.com/technical/tech.html [30] Stephen H. Hall, Garrett W. Hall, and James A. McCall, High-Speed Digital System Design, New York: John Wiley & Sons, 2000. [31] Agilent Technologies, Technical Support, Training & Events, Seminar Materials, Eye Diagram Measurements in Advanced Design System. http://www.home.agilent.com/agilent/home.jspx?cc=US&lc=eng | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/43874 | - |
dc.description.abstract | 本篇論文提出一個使用了耦合電感於三維積體電路的晶片間連接。跟電容耦合相比,電感耦合的連接有比較遠的通訊距離,我設計的距離是15 微米。較長的通訊距離意味著有較能抵抗製程上對不準的現象,而且我們使用交錯式的電感可以更進一步的克服這個問題。我們使用振幅偏移調變技術來達到信號完整的傳送。發射器包含鎖相迴路作為本地震盪器並使用電晶體開關作為被動混波器,接收器則包含了整流器來解調訊號並使用限制器放大訊號。本連接方法操作在6Gbps 時能達到4.08pJ/bit 能量效率。此無線連接使用台灣積體電路公司0.18 微米製程來驗證此電路架構。 | zh_TW |
dc.description.abstract | A wireless interconnect for 3D-IC applications is implemented by using coupled inductor design. Inductive coupling interconnect has longer communication distance as
compared with capacitive interconnect. Our communication distance is 15µm. The longer distance means that it can resist the alignment mismatches and increase the yields for packaging. We also use a mis-alignment resistance coupled inductor to alleviate the alignment problem. We use ASK modulation technique to transmit the data. In transmitter,a PLL is used as the local oscillator, and switch is used as a passive mixer. In receiver,rectifiers are used to demodulate received signal, and cascaded limiters amplify the signal.This interconnect has energy efficiency of 4.08pJ/bit at 6Gbps. The proposed wireless interconnect is implemented in TSMC 0.18µm process for demonstration of this architecture. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T02:31:16Z (GMT). No. of bitstreams: 1 ntu-98-R96943126-1.pdf: 3939395 bytes, checksum: 6741370505eef4cd65e748fda0277f1f (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | 目錄
第 1 章 簡介 ........................................................................................................ 1 1.1 動機 ........................................................................................................ 1 1.2 什麼是三維積體電 路 ............................................................................ 3 1.2.1 封裝堆疊 .......................................................................................... 3 1.2.2 晶片堆疊 .......................................................................................... 4 1.2.3 晶圓堆疊 .......................................................................................... 4 1.3 已知的垂直傳輸技術 ............................................................................ 6 1.3.1 直通矽晶穿孔(through silicon via,TSV) .................................. 6 1.3.2 無線電容耦合 .................................................................................. 7 1.3.3 無線電感耦合 .................................................................................. 7 1.4 各章節簡介 ............................................................................................ 8 第 2 章 無線垂直傳輸 ........................................................................................ 9 2.1 簡介 ........................................................................................................ 9 2.2 調變和非調變的頻譜 ............................................................................ 9 2.2.1 雙旁波帶和單旁波帶調變 .............................................................. 9 2.2.2 振幅調變和角度調變 .................................................................... 12 2.2.3 數位調變(Digital modulation) ....................................................... 12 2.2.4 歸零和不歸零訊號的頻譜 ............................................................ 13 v 2.2.5 幅移鍵控調變的頻譜 .................................................................... 17 2.3 現行的無線傳輸技術 .......................................................................... 18 2.3.1 基頻傳輸(Baseband transmission) ................................................. 18 2.3.2 幅移鍵控調變傳輸 ........................................................................ 21 2.3.3 以往的設計方法 ............................................................................ 22 第 3 章 無線連接設計 ...................................................................................... 24 3.1 幅移鍵控調變的電感耦合連接 .......................................................... 24 3.2 通道設計 .............................................................................................. 25 3.2.1 無線寬頻通道實現 ........................................................................ 25 3.2.2 對不準問題的改善 ........................................................................ 36 3.3 發射端(transmitter)和接收端(receiver)電路 ....................................... 45 3.3.1 發射端電路 .................................................................................... 45 3.3.2 接收端電路 .................................................................................... 56 3.4 佈局圖 .................................................................................................. 60 第 4 章 效能和量測 .......................................................................................... 62 4.1 抖動和眼圖 .......................................................................................... 62 4.2 模擬結果 .............................................................................................. 68 4.3 量測步驟 .............................................................................................. 70 4.3.1 發射端量測步驟 ............................................................................ 70 4.3.2 接收端量測 .................................................................................... 70 4.3.3 無線連接量測 ................................................................................ 70 4.4 [19]的晶片的量測結果 ....................................................................... 71 vi 4.4.1 發射端電路量測結果 .................................................................... 71 4.4.2 接收端電路量測結果 .................................................................... 73 第 5 章 結論 ...................................................................................................... 75 參考文獻 .................................................................................................................. 78 | |
dc.language.iso | zh-TW | |
dc.title | 應用於3D-IC並使用垂直耦合電感之晶片間的高速無線連接 | zh_TW |
dc.title | High speed wireless inter-chip signal interconnect using vertical coupled inductors for 3D-IC applications | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 吳宗霖,陳怡然,林坤佑,林宗賢 | |
dc.subject.keyword | 高速無線連接, | zh_TW |
dc.subject.keyword | 3D IC, | en |
dc.relation.page | 81 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2009-08-17 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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