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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳少傑(Sao-Jie Chen) | |
| dc.contributor.author | Shih-Hsin Lo | en |
| dc.contributor.author | 羅士欣 | zh_TW |
| dc.date.accessioned | 2021-06-15T02:27:43Z | - |
| dc.date.available | 2012-08-20 | |
| dc.date.copyright | 2009-08-20 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-08-17 | |
| dc.identifier.citation | [1] L. Benini, and G. De Micheli, “Networks in Chips: A New SoC Paradigm,” IEEE Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
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Das, “ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers,” Proceedings of International Symposium on Microarchitecture, pp. 333-346, Dec. 2006. [15] M. Lai, Z. Wang, L. Gao, H. Lu and K. Dai, “A dynamically-allocated virtual channel architecture with Congestion Awareness for On-Chip Routers,” Proceedings of Design Automation Conference, pp. 630-633, June 2008. [16] A. Kumar, P. Kundu, A. Singh, L. S. Peh and N. K. Jha, “A 4.6Tbits/s 3.6GHz Single-cycle NoC Router with a Novel Switch Allocator in 65nm CMOS,” Proceedings of International Conference on Computer Design, pp. 63-70, Oct. 2007. [17] M. Millberg, E. Nilsson, R. Thid and A. Jantsch, “Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip,” Proceedings of Design Automation and Test in Europe Conference and Exhibition, vol. 2, pp. 890-895, Feb. 2004. [18] K. Goossens, J. Dielissen, and A. Radulescu, “The Æthereal network on chip: Concepts, architectures, and implementations,” IEEE Design & Test of Computers, vol. 22, no.5, pp. 414-421, Oct. 2005. [19] E. Rijpkema, K. Goossens, A. Radulescu, J. Dielissen, J. V. Meerbergen, P. Wielage and E. Waterlander, “Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip,” IEE Proceedings of Computers and Digital Techniques, vol. 150, no.5, pp. 294- 302, Sept. 2003. [20] N. Kavaldjiev, G. J. M. Smit, P. G. Jansen and P. T. Wolkotte, “A virtual channel network-on-chip for GT and BE traffic,” Proceedings of IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, pp. 211-216, Mar. 2006. [21] M. D. Harmanci, N. P. Escudero, Y. Leblebici and P. Ienne, “Providing QoS to connection-less packet-switched NoC by implementing DiffServ functionalities,” Proceedings of International Symposium on System-on-Chip, pp. 37-40, Nov. 2004. [22] E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, “QNoC: QoS architecture and design process for network on chip,” Elsevier Journal of Systems Architecture, vol. 50, no. 2-3, pp. 105- 128, Feb. 2004. [23] Z. Guz, E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, “Efficient Link Capacity and QoS Design for Network-on-Chip,” Proceedings of Design Automation and Test in Europe, vol. 1, pp. 1- 6, Mar. 2006. [24] M. D. Harmanci, N. P. Escudero, Y. Leblebici and P. Ienne, “Quantitative modelling and comparison of communication schemes to guarantee Quality-of-Service in Networks-on-Chip,” IEEE International Symposium on Circuits and Systems, vol. 2, pp. 1782- 1785, May 2005. [25] D. Bertozzi, A. Jalabert, S. Murali, R. Tamhankar, S. Stergiou, L. Benini and G. D. Micheli, “NoC synthesis flow for customized domain specific multiprocessor systems-on-chip,” IEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 2, pp. 113-129, Feb. 2005. [26] T. Bjerregaard and S. Mahadevan, “A Survey of Research and Practices of Network-on-Chip,” ACM Computing Surveys, vol. 38, no. 1, pp. 1-51, Mar. 2006. [27] U. Orgas, J. Hu, and R. Marculescu, “Key Research Problems in NoC Design: A Holistic Perspective,” Proceedings of Hardware/Software Codesign and System Synthesis, pp. 69-74, Sept. 2005. [28] R. Marculescu, U. Y. Ogras, L. S. Peh, N. E. Jerger and Y. Hoskote, “Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 1, pp. 3-21, Jan. 2009. [29] H. G. Lee, N. Chang, U. Y. Ogras and R. Marculescu, “On-Chip Communication Architecture Exploration: A Quantitative Evaluation of Point-to-Point, Bus and Network-on-Chip Approaches,” ACM Transactions on Design Automation of Electronic Systems, vol. 12, no. 3, pp. 1-20, Aug. 2007. [30] J. Lillis and C. Cheng, “Timing Optimization for Multisource Nets: Characterization and Optimal Repeater Insertion,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 3, pp. 322-331, Mar. 1999. [31] A. Nalamalpu, S. Srinivasan, and W. P. Burleson, “Boosters for Driving Long Onchip Interconnects – Design Issues, Interconnect Synthesis, and Comparison with Repeaters,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 1, pp. 50-62, Jan. 2002. [32] S. Bobba and I. N. Hajj, “High-Performance Bidirectional Repeaters,” Proceedings of Great Lakes Symposium on VLSI, pp. 53-58, Mar. 2000. [33] D.C. Gazis, Traffic Science, John Wiley & Sons, 1974. [34] R. Dick, “Embedded System Synthesis Benchmark Suites (E3S),” http://ziyang.eecs.umich.edu/~dickrp/e3s/, accessed Jan. 2009. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/43754 | - |
| dc.description.abstract | 本文提出一個使用雙向通道的晶片網路架構，它同時支援了不同服務品質的資料傳輸，使得晶片內部的傳輸效能有所改善。此雙向的晶片網路架構允許每一條通道能夠動態的自我調整傳送方向來提高晶片內硬體資源的利用率。對於每一個晶片網路的路由器而言，資料通訊的延遲時間，傳輸吞吐量，以及頻寬利用率都受到這個附加的通道靈活性影響而得到更好的效能。這篇論文呈現出一個創新的路由器架構設計以及一個控制雙向通道的機制。透過分析可以證明此架構的額外硬體成本是可忽略的。本文利用一個精準時脈週期的測試環境進行模擬，對於在假想的交通型態以及真實規格的傳輸情況下，此雙向通道的晶片網路相對於傳統的單向通道架構都能展現出可觀的效能優勢。 | zh_TW |
| dc.description.abstract | A Bidirectional channel Network-on-Chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication while supporting prioritized traffics in the network. The BiNoC allows each communication channel to be dynamically self-configured to transmit flits in either direction in order to better utilize on-chip hardware resources. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate at each on-chip router. In this Thesis, a novel on-chip router architecture supporting the self-configuring bidirectional channel mechanism is presented. It is shown that the associated hardware overhead is negligible. Cycle-accurate simulation runs on this BiNoC network under synthetic and real-world traffic patterns demonstrate consistent and significant performance advantage over a conventional mesh grid NoC architecture equipped with hard-wired unidirectional channels. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T02:27:43Z (GMT). No. of bitstreams: 1 ntu-98-R96943130-1.pdf: 1535169 bytes, checksum: 586070a98dcd2f28d98ef9b476066ee5 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | ABSTRACT i
LIST OF FIGURES v LIST OF TABLES vii CHAPTER 1 INTRODUCTION 1 1.1 Current Trends in On-chip Communication 1 1.1.1 Conventional Communication Schemes in System-on-Chip 2 1.1.2 The Emergence of Network-on-Chip 3 1.2 Concept of Network-on-Chip 4 1.2.1 Different Layers in a Network-on-Chip Design 4 1.2.2 Network-on-Chip Architecture 6 1.3 Network Basics 7 1.3.1 Routing 7 1.3.2 Flow Control 8 1.3.3 Performance Evaluation 9 1.4 Quality-of-Service 10 1.5 Thesis Organization 12 CHAPTER 2 BACKGROUND KNOWLEDGE 13 2.1 Design of Router Architecture 13 2.2 Virtual Channel Flow Control 21 2.3 Quality-of-Service in Network-on-Chip 26 CHAPTER 3 BIDIRECTIONAL NOC ARCHITECTURE 29 3.1 Motivation 29 3.2 Related Work 30 3.3 Self-Reconfigurable Routing Scheme 31 3.3.1 NoC Architecture 31 3.3.2 Problem Formulation 31 3.3.3 Inter-Router Transmission Scheme 34 3.3.4 Bidirectional Channel Control Logic 35 3.3.5 Example of Bidirectional Transmission 38 3.4 Router Architecture 41 3.4.1 Conventional Router Architecture 41 3.4.2 Bidirectional Channel Router Architecture 43 CHAPTER 4 ROUTER ARCHITECTURE WITH QOS SUPPORT 47 4.1 Virtual Channel Router in BiNoC 47 4.1.1 Virtual Channel Router Model 47 4.1.2 Virtual Channel Allocation 49 4.1.3 Switch Allocation 51 4.1.4 Architecture of Virtual Channel Router in BiNoC 53 4.2 QoS Support in BiNoC 56 4.2.1 Basic Connection-less Scheme in Typical NoC 56 4.2.2 Proposed Connection-less Scheme in BiNoC 59 CHAPTER 5 EXPERIMENTAL RESULTS AND DISCUSSION 65 5.1 Performance Evaluation on Virtual Channel Routers 65 5.1.1 Synthetic Traffic Analysis 66 5.1.2 Experiments with Real Applications 75 5.2 Performance Evaluation on QoS Mechanisms 80 5.3 Estimation on Implementation Overhead 84 CHAPTER 6 CONCLUSION 85 REFERENCE 87 | |
| dc.language.iso | en | |
| dc.subject | 服務質量 | zh_TW |
| dc.subject | 晶片網路 | zh_TW |
| dc.subject | 路由器 | zh_TW |
| dc.subject | 雙向通道 | zh_TW |
| dc.subject | 虛擬通道 | zh_TW |
| dc.subject | Network-on-Chip | en |
| dc.subject | Quality-of-Service | en |
| dc.subject | Virtual Channel | en |
| dc.subject | Bidirectional Channel | en |
| dc.subject | Router | en |
| dc.title | 一個可動態調整通道的晶片網路架構設計 | zh_TW |
| dc.title | Design of a Network-on-Chip Architecture with Dynamically Reconfigurable Channels | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 吳安宇,盧亦璋,熊博安 | |
| dc.subject.keyword | 晶片網路,路由器,雙向通道,虛擬通道,服務質量, | zh_TW |
| dc.subject.keyword | Network-on-Chip,Router,Bidirectional Channel,Virtual Channel,Quality-of-Service, | en |
| dc.relation.page | 90 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2009-08-17 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-98-1.pdf 未授權公開取用 | 1.5 MB | Adobe PDF |
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