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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
| dc.contributor.author | Li-Han Hung | en |
| dc.contributor.author | 洪立翰 | zh_TW |
| dc.date.accessioned | 2021-06-15T02:23:29Z | - |
| dc.date.available | 2010-08-20 | |
| dc.date.copyright | 2009-08-20 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-08-18 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/43563 | - |
| dc.description.abstract | 管線式類比數位轉換器已被廣泛地使用在中解析度且高速的應用中。本論文中提出一個以「分割」類比數位轉換器為基礎的背景數位校正技術，用以修正管線式類比數位轉換器中的線性誤差，這使得結構簡單、低增益的運算放大器可以被使用在轉換級中。所設計的類比數位轉換器，其原始數位碼輸出的SNDR與SFDR 表現僅有35.3 dB與37.3 dBFS。隨著相關的線性誤差由提出的校正技術以可適性方式移除，其SNDR與SFDR提昇至55.2 dB與67.0 dBFS的水準。此外，在五千萬赫茲轉換速率下，所提出的校正系統收斂耗時少於十毫秒，與先前文獻相比，有著大幅的改善。
採用0.35微米CMOS製程製作，此「分割」管線式類比數位轉換器核心面積為1.64平方毫米。運算放大器共享技巧的引入，在三伏供應電壓、五千萬赫茲轉換速率下，將核心消耗的功率降低至四十五毫瓦。在本論文的最後，發展出一個結合線性逼近與「分割」概念的非線性校正技術，用以增進使用開路放大器建構的管線式類比數位轉換器之解析度。 | zh_TW |
| dc.description.abstract | Pipelined analog-to-digital converters (ADCs) have been widely utilized in mid-resolution, high-speed applications. In this thesis, a background digital calibration technique based on the split ADC is proposed to correct linear errors in a pipelined ADC, which allows the use of simple-structured low-gain opamps in conversion stages. Raw output codes of the designed ADC exhibit a SNDR and a SFDR of merely 35.3 dB and 37.3 dBFS, respectively. As the associated linear errors are adaptively removed by the proposed calibration technique, the SNDR and the SFDR are improved to the level of 55.2 dB and 67 dBFS. Furthermore, the proposed calibration system converges in less than 10ms at 50MS/s, showing a significant improvement over previous works.
Fabricated in the 0.35um CMOS technology, the core this split pipelined ADC occupies 1.64mm2. The introducing of opamp-sharing technique reduces the core power consumption to 45mW from a 3V supply voltage at 50MS/s. At the end of this thesis, a nonlinear calibration technique combining the linear approximation and the split concept is developed to enhance the resolution for pipelined ADCs realized with open-loop amplifiers. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T02:23:29Z (GMT). No. of bitstreams: 1 ntu-98-R95943040-1.pdf: 6000614 bytes, checksum: d002596f11b18c4650fe8d1b8fd95097 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | 口試委員審定書(中/英)
誌謝 i 摘要 iii Abstract iv Contents v List of Figures ix List of Tables xv Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 4 Chapter 2 Fundamentals of Analog-to-Digital Converters 7 2.1 Introduction 7 2.2 ADC Performance Metrics 7 2.2.1 Differential and Integral Nonlinearity (DNL, INL) 7 2.2.2 Signal-to-Noise Ratio (SNR) 10 2.2.3 Aperture Jitter and Thermal Noise 11 2.2.4 Signal-to-Noise-and-Distortion Ratio (SNDR) 13 2.2.5 Effective Number-of-Bits (ENOB) 14 2.2.6 Spurious-Free Dynamic Range (SFDR) 14 2.2.7 Figure of Merit (FoM) 15 2.3 Architectures of Analog-to-Digital Converters 16 2.3.1 Flash ADC 16 2.3.2 Two-Step and Sub-Ranging ADC 17 2.3.3 Folding ADC 18 2.3.4 Pipelined ADC 19 2.3.5 Cyclic (Algorithmic) ADC 20 2.3.6 Successive-Approximation ADC 21 2.4 Summary 22 Chapter 3 A Split Calibration Technique in Pipelined ADCs 23 3.1 Introduction 23 3.2 Building Blocks of Pipelined ADC 23 3.2.1 Conversion Stage 23 3.2.2 Digital Redundancy and Error Correction 26 3.3 Non-ideality Considerations in MDAC 28 3.3.1 Offset, Gain, and Nonlinearity Errors of SDAC 29 3.3.2 Offset, Gain, and Nonlinearity Errors of Residue Gain 31 3.3.3 Offset, Gain, and Nonlinearity Errors of S/H 32 3.3.4 Relating Error Terms to SC-MDAC 32 3.4 “Split” Digital Calibration Techniques 34 3.4.1 Overview of digital calibration schemes 34 3.4.2 Concept of “Split” 36 3.4.3 Split calibration for linear gain errors 38 3.4.4 Split calibration for capacitor-mismatch errors 43 3.4.5 Gain and Offset Mismatches 44 3.5 Power Reduction Schemes 46 3.5.1 Opamp Sharing 46 3.5.2 Opamp Switching 48 3.6 Summary 50 Chapter 4 Circuit Implementation of Split Pipelined ADC 51 4.1 Introduction 51 4.2 Analog Building Blocks 52 4.2.1 Sample-and-Hold Circuit 53 4.2.2 Front-end Conversion Stages 59 4.2.3 Backend Conversion Stages 63 4.2.4 Bias Generation and Distribution 66 4.2.5 Clock Generation 69 4.3 Digital Calibration Blocks 70 4.4 Simulation Results of Split Pipelined ADC 73 4.5 Layout & Floor-plan Considerations 76 4.5.1 Clock distribution 76 4.5.2 Capacitor and resistor matching 77 4.5.3 Floor-plan of 1.5-bit conversion stages 78 4.5.4 Layout of split pipelined ADC 80 4.6 Summary 81 Chapter 5 Experimental Results 83 5.1 Introduction 83 5.2 Post-Layout Simulations 83 5.3 Print Circuit Board Design 84 5.4 Measurement Setup 90 5.5 Measurement Results 92 5.6 Summary 97 Chapter 6 Linear Approximation on Nonlinear Gain Errors 99 6.1 Introduction 99 6.2 Characterizing basic differential pairs 100 6.3 Split Calibration for nonlinear gain errors 104 6.3.1 Piecewise linear approximation 104 6.3.2 Non-ideal backend ADC effects 107 6.3.3 Approximation compared with analytical form 108 6.4 System-level Implementation 110 6.5 Summary 113 Chapter 7 Conclusions and Future Works 115 7.1 Conclusions 115 7.2 Future Works 116 Bibliography 117 Biography | |
| dc.language.iso | en | |
| dc.title | 應用放大器共享技巧並輔以分割背景數位校正之十位元五千萬赫茲管線式類比數位轉換器 | zh_TW |
| dc.title | A 10-bit 50-MS/s Pipelined A/D Converter with Split Background Digital Calibration and Opamp-Sharing Technique | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳巍仁(Wei-Zen Chen),林宗賢(Tsung-Hsien Lin),陳信樹(Hsin-Shu Chen) | |
| dc.subject.keyword | 可適性系統,類比數位轉換,背景數位校正,運算放大器共享技巧,管線式類比數位轉換器, | zh_TW |
| dc.subject.keyword | adaptive systems,analog-to-digital conversion,background digital calibration,opamp-sharing technique,pipelined analog-to-digital converters, | en |
| dc.relation.page | 125 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2009-08-18 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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