應用放大器共享技巧並輔以分割背景數位校正之十位元五千萬赫茲管線式類比數位轉換器

Abstract

管線式類比數位轉換器已被廣泛地使用在中解析度且高速的應用中。本論文中提出一個以「分割」類比數位轉換器為基礎的背景數位校正技術，用以修正管線式類比數位轉換器中的線性誤差，這使得結構簡單、低增益的運算放大器可以被使用在轉換級中。所設計的類比數位轉換器，其原始數位碼輸出的SNDR與SFDR 表現僅有35.3 dB與37.3 dBFS。隨著相關的線性誤差由提出的校正技術以可適性方式移除，其SNDR與SFDR提昇至55.2 dB與67.0 dBFS的水準。此外，在五千萬赫茲轉換速率下，所提出的校正系統收斂耗時少於十毫秒，與先前文獻相比，有著大幅的改善。 採用0.35微米CMOS製程製作，此「分割」管線式類比數位轉換器核心面積為1.64平方毫米。運算放大器共享技巧的引入，在三伏供應電壓、五千萬赫茲轉換速率下，將核心消耗的功率降低至四十五毫瓦。在本論文的最後，發展出一個結合線性逼近與「分割」概念的非線性校正技術，用以增進使用開路放大器建構的管線式類比數位轉換器之解析度。

Pipelined analog-to-digital converters (ADCs) have been widely utilized in mid-resolution, high-speed applications. In this thesis, a background digital calibration technique based on the split ADC is proposed to correct linear errors in a pipelined ADC, which allows the use of simple-structured low-gain opamps in conversion stages. Raw output codes of the designed ADC exhibit a SNDR and a SFDR of merely 35.3 dB and 37.3 dBFS, respectively. As the associated linear errors are adaptively removed by the proposed calibration technique, the SNDR and the SFDR are improved to the level of 55.2 dB and 67 dBFS. Furthermore, the proposed calibration system converges in less than 10ms at 50MS/s, showing a significant improvement over previous works. Fabricated in the 0.35um CMOS technology, the core this split pipelined ADC occupies 1.64mm2. The introducing of opamp-sharing technique reduces the core power consumption to 45mW from a 3V supply voltage at 50MS/s. At the end of this thesis, a nonlinear calibration technique combining the linear approximation and the split concept is developed to enhance the resolution for pipelined ADCs realized with open-loop amplifiers.