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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳光禎(Kwang-Cheng Chen) | |
| dc.contributor.author | Ching-Kai Liang | en |
| dc.contributor.author | 梁景凱 | zh_TW |
| dc.date.accessioned | 2021-06-15T02:22:19Z | - |
| dc.date.available | 2009-08-20 | |
| dc.date.copyright | 2009-08-20 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-08-19 | |
| dc.identifier.citation | [1] K.C.Chen, Y.J. Peng, N.Prasad, Y.C.Liang and S.Sun, “Cognitive radio network architecture: part I -- general structure,” In Procc. 2nd international Conference on Ubiquitous information Management and Communication (ICUIMC), 2008.
[2] J. Mitola III, and G. Q. Maguire, “Cognitive Radio: Making Software Radios More Personal,” IEEE Personal Communications, vol.6, no.4, pp.13-18, Aug 1999. [3] J. Mitola III. “Cognitive Radio Architecture,” Wiley, 2006. [4] http://www.srdforum.org/ [5] K. C. Chen and S. T. Wu, 'A Programmable Architecture for OFDM-CDMA,' Communications Magazine, IEEE , vol.37, no.11, pp.76-82, Nov 1999 [6] M. H. Wu, “A Reconfigurable Architecture for OFDM-based Wireless Communication Systems,” MS Thesis, National Taiwan University, Taipei, 2005. [7] R. Baines, and D. Pulley, 'A Total Cost Approach to Evaluating Different Reconfigurable Architectures for Baseband Processing in Wireless Receivers,' Communications Magazine, IEEE , vol.41, no.1, pp. 105-113, Jan 2003. [8] Z. Salcic, and C.F. Mecklenbrauker, 'Software Radio - Architectural Requirements, Research and Development Challenges,' The 8th International Conference on Communication Systems, vol.2, no., pp. 711-716 vol.2, 25-28 Nov. 2002. [9] S. Rajagopal, “Communication Processors,” Wiley encyclopedia of computer science and engineering , July. 2005. [10] J. Bjorkqvist, and S. Virtanen, 'Convergence of Hardware and Software in Platforms for Radio Technologies,' IEEE Communications Magazine, vol.44, no.11, pp.52-57, November 2006. [11] M. S. Safadi, and D. L. Ndzi, 'Digital Hardware Choices For Software Radio (SDR) Baseband Implementation,' Information and Communication Technologies, vol.2, pp.2623-2628, 2006. [12] M Eteläperä and JP Soininen, “4G Mobile Terminal Architectures,” VTT ROOSTER project, 2007. [13] H. Arslan, and H. Celebi, “Software Defined Radio Architectures for Cognitive Radios,” Cognitive Radio, Software Defined Radio, and Adaptive Wireless Systems, 109–144, Springer, 2007. [14] U. Ramacher, 'Software-Defined Radio Prospects for Multistandard Mobile Phones,' Computer , vol.40, no.10, pp.62-69, Oct. 2007. [15] S. Vassiliadis et al., “Trends in Low Power Handset Software Defined Radio,” Embedded Computer Systems: Architectures, Modeling, and Simulation, pp313-321, Springer, 2007. [16] Min Li, B. Bougard, D. Novo, L. Van Der Perre, and F. Catthoor, 'How to let Instruction Set Processor Beat ASIC for Low Power Wireless Baseband Implementation: A System Level Approach,' ACM/IEEE Design Automation Conference, 2008. [17] A. Nilsson, E. Tell, and D. Liu, “An Accelerator Architecture for Programmable Multi-Standard Baseband Processors,” in Proc. Int. zonf. Wireless Networks and Emerging Technologies, Banff, Canada, Jul. 2004. [18] E. Tell, A. Nilsson, and D. Liu, 'A Low Area and Low Power Programmable Baseband Processor Architecture,' System-on-Chip for Real-Time Applications, 2005. Proceedings. Fifth International Workshop on, July 2005 [19] K. S. Raju, M. V. Kartikeyan, R. C. Joshi, C. Shekhar, 'Design of Architecture and Instruction-set of RASIP for SDR,' Advanced Computing and Communications, 2006. ADCOM 2006. International Conference on , pp.493-496, 20-23 Dec. 2006. [20] J. Glossner, D. Iancu, M. Moudgill, G. Nacer, S. Jinturkar, S. Stanley, and M. Schulte, “The Sandbridge SB3011 Platform”, EURASIP J. Embedded Syst., no. 1, pp. 16.16, 2007 [21] S. Mamidi, M. J. Schulte, Zaipeng Xie; M. Sima, D. Iancu, and J. Glossner, 'Arithmetic Units for Software Defined Radio,' Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on , pp.341-346, Oct. 29 2006-Nov. 1 2006. [22] C. Grassmann, M. Richter, and M. Sauermann, 'Mapping the Physical Layer of Radio Standards to Multiprocessor Architectures,' Design, Automation & Test in Europe Conference & Exhibition, pp.1-6, 16-20 April 2007. [23] D. C. Cronquist, C. Fisher, M. Figueroa, P. Franklin, and C. Ebeling, “Architecture Design of Reconfigurable Pipelined Datapaths,” Proc. Conf. Advanced Research in VLSI, pp. 23-40, 1999. [24] D.C. Ebeling, C. Fisher, G. Xing, M. Shen, and H. Liu, “Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture,” IEEE Trans. on Computers, pp. 1436-1448, Nov. 2004 [25] A. Kamalizad, N. Tabrizi, N. Bagherzadeh, and A. Hatanaka, 'A Programmable DSP Architecture for Wireless Communication Systems,' 16th IEEE International Conference on Application-Specific Systems, Architecture Processors, pp. 231-238, 23-25 July 2005 [26] N. Tabrizi, N. Bagherzadeh, A. H. Kamalizad, H. Du, “MaRS: A Macro-pipelined Reconfigurable System,” Proc. Of the First Conference on Computing Frontiers, Ischia, pp. 343-349, April 2004. [27] Poon, A.S.Y., 'An Energy-Efficient Reconfigurable Baseband Processor for Wireless Communications,' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.15, no.3, pp.319-327, March 2007. [28] B. Bougard, B. De Sutter, S. Rabou, D. Novo, O. Allam, S. Dupont and L. Van der Perre, “A Coarse-Grained Array based Baseband Processor for 100 Mbps+ Software Defined Radio,” Design, Automation and Test in Europe, pp. 716–721., 2008 [29] B. Bougard, B. De Sutter, D. Verkest, L. Van der Perre, R. Lauwereins, 'A Coarse-Grained Array Accelerator for Software-Defined Radio Baseband Processing,' Micro, IEEE , vol.28, no.4, pp.41-50, July-Aug. 2008. [30] Texas Instruments, DSP platforms benchmarks, Tech. Rep., http://www.ti.com/. [31] C. Kozyrakis, “Vector vs. Superscalar and VLIW Architectures for Embedded Multimedia Benchmarks,” In Micro , pp. 283–289, Nov., 2002. [32] T. Lin, and C. Jen, “CASCADE—Configurable and scalable DSP environment,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 26–29, May, 2002. [33] Yu Z., et al., “Architecture and Evaluation of an Asynchronous Array of Processors,” Journal of Signal Process Systems, 2008. [34] J. M. Rabaey. “Low-Power Silicon Architectures for Wireless Communications,” in Design Automation Conference ASP-DAC 2000, Asia and South Pacific Meeting, pp 377-380. Yokohama, Japan, Jan. 2000. [35] J.-J. V. Beek, O. Edfors, M. Sandell, S. K. Wilson, and P. O. Borjesson: “On Channel Estimation in OFDM Systems,” Vehicular Technology Conference, vol.2, July 1995. [36] M. Morelli, C.-C. Kuo, and M.-O. Pun, “Synchronization techniques for orthogonal frequency division multiple access (OFDMA): A tutorial review,” Proceedings of the IEEE, vol. 95, no. 7, pp. 1394–1427, July 2007. [37] A.L. Cinquino, Y.R. Shayan, “A Real-Time Software Implementation of an OFDM Modem Suitable for Software Defined Radios,” Canadian Conference on Electrical and Computer Engineering, vol. 2, pp. 697- 701, May 2004. [38] R. Baines, 'The DSP Bottleneck,' IEEE Communications Magazine, vol.33, no.5, pp.46-54, May 1995 [39] D. Chinnery, et al., “Closing the Gap Between ASIC & Custom : An ASIC Perspective,“ Kluwer Academic Publishers, 2002. [40] N. Zhang, and R.W. Brodersen, 'Architectural Evaluation of Flexible Digital Signal Processing for Wireless Receivers,' 34th Asilomar Conference on Signals, Systems and Computers, vol.1, no., pp.78-83 vol.1, 2000. [41] B. Salefski, and L. Caglar., “Re-configurable Computing in Wireless,” In Proc. 38th Design Automation Conference, Las Vegas, NV, 2001. [42] H. Lee et al., “Software Defined Radio - A High Performance Embedded Challenge,” In Proc. 2005 Intl. Conference on High Performance Embedded Architectures and Compilers (HiPEAC), Nov. 2005 [43] R. Enzler, “Architectural Trade-offs in Dynamically Reconfigurable Processors,“ Ph.D Dissertation, Swiss Federal Institute of Technology, ETH Zurich, 2004. [44] J. P. Robelly, H. Seidel, K.C. Chen, and Fettweis, G., 'Energy Efficiency vs. Programmability Trade-off: Architectures and Design Principles,' Proceedings on Design, Automation and Test in Europe, vol.1, no., pp.1-6, 6-10 March 2006. [45] J. M. Rabaey, “Low-Power Silicon Architectures for Wireless Communications,” ASP-DAC pp. 77-80, 2000. [46] K. Masselos, S. Blionas, and T. Rautio, “Reconfigurability Requirements of Wireless Communication Systems,” In Proceedings of the IEEE Workshop on Heterogeneous Reconfigurable Systems on Chip, Hamburg, Germany, April 2002. [47] R. Enzler, C. Plessl, and M. Platzner, “System-Level Performance Evaluation of Reconfigurable Processors,” Microprocessors and Microsystems, 29(issues 2–3):63–73, Apr. 2005. [48] A. Nilsson, E. Tell, and D. Liu, ”Simultaneous Multi-standard Support in Programmable Baseband Processors,” Proc. IEEE PRIME, 2006. [49] Harju, L.; Nurmi, J., 'A Programmable Baseband Receiver Platform for WCDMA/OFDM Mobile Terminals,' IEEE Wireless Communications and Networking Conference, Vol. 1, pp. 33-38, 13-17 March 2005. [50] M. B. Taylor, et al., “The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs,” IEEE Micro, pp. 25–35, Mar 2002. [51] M. B. Taylor, J. Psota, A. Saraf, N. Shnidman, V. Strumpen, M. Frank, S. Amarasinghe, A. Agarwal, W. Lee, J. Miller, D. Wentzlaff, I. Bratt, B. Greenwald, H. Hoffmann, P. Johnson, and J. Kim, 'Evaluation of the Raw Microprocessor: An Exposed-Wire-delay Architecture for ILP and Streams,' Proceedings. 31st Annual International Symposium on Computer Architecture, pp. 2-13, 19-23 June 2004. [52] G. K. Rauwerda, P. M. Heysters, and G. J. M. Smit, 'Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware,' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16, no.1, pp.3-13, Jan. 2008. [53] K. Maharatna, E. Grass, and U. Jagdhold, “A 64-point Fourier Transform Chip for High-Speed Wireless LAN Application Using OFDM,” IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 484–493, Mar. 2004. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/43488 | - |
| dc.description.abstract | 隨著科技的進步，行動裝置的功能越來越強，也讓一個手持裝置可能同時支援許多無線通訊系統。現今的做法都是整合許多專用集成電路，一個負責一種通訊協定，來提供所需的多種傳輸模式功能。然而，當越來越多的通訊協定必須加入到一個手持裝置時，這就不再是一個非常有效率而且足夠彈性的做法。軟體無線電技術就是希望利用一個可程式化的處理器來即時的重新編組以切換所支援的無線通訊系統。隨著未來的通訊系統複雜度越來越高，可編程的處理器必須提供每秒一千億個運算能力才能符合需求，而現今主流的超長指令字訊號處理器卻無法提供這樣的運算能力。因此，我們需要研究一種新的架構能同時符合龐大的運算能力要求但又能提供足夠的編程彈性。可重置架構因為可以有效的利用許多運算元因而被嚐試應用到軟體無線電中。而其運算元從簡單的一個算術邏輯元件到完整的一個處理器都涵括在可重置架構的範疇中。我們在這篇論文中就分析了一些常見的通訊演算法，並提出一個基於可重置架構的通訊處理器。我們將所有的算術邏輯元件以一個共同的數據傳輸線連結起來，形成一個在邏輯上排列成一維陣列的架構。此架構非常適合用於運算有限脈衝響應濾波器之實現以及一些矩陣運算。另外，此架構也包含一個可編程的資料交換傳輸線，能有效的將運算元中的暫存資料做交換。 | zh_TW |
| dc.description.abstract | Nowadays, mobile devices are incorporated with more and more communication standards. Currently, several ASICs are combined to support the multi-mode operation in a mobile device. However, this is neither an efficient nor a flexible solution when more radio interfaces are added. Software-Defined Radio tends to use programmable processors to reconfigure on the fly and switch from one radio interface to another. With future communication standards having computation complexity up to 100s and even 1000s of GOPS, current DSP processors with VLIW architecture will not be able to meet the real-time requirements. This requires the research for a more suitable architecture for communication related algorithms. Coarse-grained reconfigurable architectures have gain attention in the application of SDR. This class of processors embeds a large amount of processing units arranged in a 1D/2D array. The granularity of processing elements spreads over a wide range, from an ALU to a simple RISC processor.
They tend to provide t of processing power by incorporating many functional units. Inspired by reconfigurable architectures, we propose architecture consists of a wide 1D ALU array, which tends to compute each operation related to the input data simultaneous. This kind of computation is suitable for FIR filtering, matrix-vector multiplications and other digital communication algorithms. A global data bus is used to broadcast inputs to all PEs and a reconfigurable data exchange bus is utilized to pass data between ALUs, which tends to compute each operation related to the input data simultaneous. This kind of computation is suitable for FIR filtering, matrix-vector multiplications and other digital communication algorithms. A global data bus is used to broadcast inputs to all PEs and a reconfigurable data exchange bus is utilized to pass data between ALUs. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T02:22:19Z (GMT). No. of bitstreams: 1 ntu-98-R96942037-1.pdf: 1058499 bytes, checksum: 092be5914948ec72f7c43ca941a56ffc (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | 誌謝....................................................I
摘要....................................................II Abstract................................................III List of Figures.........................................VIII List of Tables..........................................X Chapter 1 Introduction..................................1 1.1 Motivation.........................................1 1.2 Software Defined Radio and Communication Processor.2 1.3 Organization.......................................4 Chapter 2 Survey of Communication Processors............5 2.1 Single DSP Processor with Accelerators.............5 2.2 Multi-core DSP Processors..........................7 2.2.1 Sandbridge Sandblast Processor..................7 2.2.2 MuSIC Baseband Processor........................9 2.3 Reconfigurable Architecture........................11 2.3.1 RaPid Architecture..............................11 2.3.2 MaRS Architecture...............................13 2.4 Heterogeneous Architecture.........................15 2.5 Comparison and Summary.............................17 Chapter 3 Analysis of Communication Algorithms..........19 3.1 FIR Filtering......................................20 3.2 Correlation Calculation............................21 3.3 Fast Fourier Transform (FFT).......................23 3.4 QAM Demodulation...................................25 3.5 Viterbi Algorithm..................................26 3.6 Summary............................................30 Chapter 4 Proposed Communication Processor..............32 4.1 Design Philosophy..................................33 4.2 Architecture Overview..............................37 4.3 Instruction Set....................................38 4.4 Pipeline Data Path.................................41 4.4.1 Data Fetch Controller...........................41 4.4.2 Processing Element..............................43 4.4.3 Inter-PE Communication & Data/Instruction Bus...45 4.5 Summary............................................46 Chapter 5 Algorithm Mapping.............................48 5.1 Mapping of FIR Filter..............................48 5.2 Mapping of Auto-Correlation........................50 5.3 Mapping of FFT.....................................52 5.4 Mapping of Viterbi Decoding........................54 5.5 Mapping of QAM Demodulation........................55 5.6 Discussion.........................................58 Chapter 6 Synthesis & Future work.......................59 6.1 Synthesis Results..................................59 6.2 Comparison with other architectures................62 6.3 Conclusion and Future Work.........................64 Bibliography............................................66 | |
| dc.language.iso | en | |
| dc.subject | 通訊處理器 | zh_TW |
| dc.subject | 軟體無線電 | zh_TW |
| dc.subject | 處理器架構 | zh_TW |
| dc.subject | 可重置架構 | zh_TW |
| dc.subject | Reconfigurable architecture | en |
| dc.subject | Communication processor | en |
| dc.subject | Software defined radio | en |
| dc.subject | Processor architecture | en |
| dc.title | 可程式化通訊處理器之架構設計與分析 | zh_TW |
| dc.title | Architecture Analysis and Design of Programmable Communication Processor | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 闕志達(Tzi-Dar Chiueh),張仲儒(Chung-Ju Chang),徐永珍(Yung-Jane Hsu),陳曉華(Hsiao-Hwa Chen) | |
| dc.subject.keyword | 軟體無線電,處理器架構,可重置架構,通訊處理器, | zh_TW |
| dc.subject.keyword | Software defined radio,Processor architecture,Reconfigurable architecture,Communication processor, | en |
| dc.relation.page | 72 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2009-08-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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