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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/43440完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭正邦 | |
| dc.contributor.author | " Lu,Jun-Yi" | en |
| dc.contributor.author | 呂俊毅 | zh_TW |
| dc.date.accessioned | 2021-06-15T01:57:02Z | - |
| dc.date.available | 2014-07-03 | |
| dc.date.copyright | 2009-07-03 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-06-26 | |
| dc.identifier.citation | [1.1]P. J. VanDerVoorn and J. P. Krusius, “Inversion Channel Edge in Trench-Isolat ed Sub-1/4-um MOSFET’s,” IEEE Trans. Elec. Dev.,43(8), 1274-1280,1996.
[1.2]H. S. Lee, M. H. Park, Y. G. Shin, T. –S. Park, H. K. Kang, S.I. Lee and M. Y. Lee, “An Optimized Densification of the Filled Oxide for Quarter Micron Shallow Trench Isolation (STI),”VLSI Tech. Dig.,158-159 , 1996. [1.3]A. Chatterjee, J. Esquivel, S. Nag, I. Ali, D. Rogers, K. Taylor, K. Joyner, M. Mason, D. Mercer, A. Amerasekera, T. Houston and I. C. Chen,“A shallow Trench Isolation Study for 0.25/0.18um CMOS Technologies and Beyond, “ VLSI Tech. Dig., 156-157. [1.4]J.-P. Colinge,“Silicon-on-Insulation Technology: Materials to VLSI, 2nd ed.“ Kluwer Academic: Boston, 1997. [1.5]K. F. Goser, C. Pacha, A. Kanstein, and M. L. Rossmann, “Aspects of Systems and Circuits for Nanoelectronics,“ Proc. Of IEEE, 85(4), 558-576, 1997. [1.6]A.O. Adan, T. Naka, A. Kagisawa, and H. Shimizu, “SOI as Mainstream IC Technology, “ SOI Conf. Dig., 9-12, 1998. [1.7]D. E. Ward and R. W. Dutton,“A Charge-Oriented Model for MOS Transistor Capacitances,”IEEE J. Solid-State Circuits, Vol.13, p.703-708, Oct 1978. [2.1]R. A. Bianchi, G. Bouche, O. Roux-dit-Buisson, “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,” IEDM Tech Dig, pp.117-120, 2002. [2.2]C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, R. Gwoziecki, S. Orain, E. Robilliart, C. Raynaud, and H. Dansas, “Electrical analysis of mechanical stress induced by STI in short MOS using externally applied stress,” IEEE Tran. Elec. Dev., vol. 51, no. 8, pp. 1254-61, Aug. 2004. [2.3]I. S. Lin, J. B. Kuo, G. S. Lin, D. C. Chen, C. S. Yeh, C. T. Tsai and M. Ma, “Breakdown behavior of 40-nm PD-SOI NMOS device considering STI-induced mechanical stress effect,” IEEE Elec. Dev. Lett., vol. 29, no. 6, pp.612-614, June 2008. [2.4]I. S. Lin, J. B. Kuo, G. S. Lin, D. C. Chen, C. S. Yeh, C. T. Tsai, and M. Ma, “STI-induced mechanical-stress-related kink effect behaviors of 40-nm PD SOI NMOS device,” IEEE Tran. Elec. Dev., vol. 55, no. 6, pp. 1558-1562, June 2008. [2.5] I. S. Lin, J. B. Kuo, D. C. Chen, C. S. Yeh, C. T. Tsai, and M. Ma,“STI-induced mechanical stress-related kink effect of 40-nm PD SOI NMOS devices,” EUROSOI, Cork, Ireland, 2008. [2.6]J. Pretet, D. Ioannon, N. Subba, S. Cristoloveanu, W. Maszara, and C. Raynaud, “Narrow-channel effects and their impact on the static and floating-body characteristics of STI- and LOCOS-isolated SOI MOSFETs,”Sol. St. Elec., vol. 46, no. 11, pp. 1699-1707, 2002. [3.1]S. S. Chen and J. B. Kuo, “Analytical Kink Effect Model of PD SOI NMOS Devices Operating in Strong Inversion,” Solid State Electronics, pp. 447-458, March 1997. [3.2] S. C. Lin and J. B. Kuo, “Temperature Dependent Kink Effect Model for PD SOI NMOS Devices,” IEEE Trans. Electron Devices, pp.254-258, Feb 1999. [3.3]J. -P. Colinge, “Reduction of Kink Effect in Thin Film SOI MOSFET’s,”IEEE Electron Device Letters, Vol.EDL-9, pp.97-99, Feb 1988. [3.4]K. Kato, T. Wada and K. Taniguchi, “Analysis of Kink Characteristics in Silicon-on-Insulator MOSFET’s Using Two-Carrier Modeling,” IEEE Trans. Electron Devices, Vol.32, No. 2, pp.458-462, Feb 1985. [3.5]S. S. Chen and J. B. Kuo, “An Analytical CAD Kink Effect Model of Partially-Depleted SOI NMOS Devices Operating in Strong Inversion,” Solid State Electronics, Vol. 41, No. 3, pp. 447-458, March 1997. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/43440 | - |
| dc.description.abstract | 本論文探討部份解離絕緣體上矽N型金氧半(PD SOI NMOS)元件之淺槽隔離對窄通道元件影響，潛槽隔離可能影響電子平均壽命，使得元件特性改變，我們量測不同通道寬度的元件來做比較。接著是討論太薄的閘極氧化層情況下，其閘極漏電流對元件本質電容的影響，模擬閘-源極電容與閘-洩極電容對於不同汲極電壓的變化，並發現部分解離絕緣體上矽N型金氧半元件底部寄生雙載子電晶體導
通時，會引發電流突增現象並且影響元件本質電容，使其產生一突跳現象，接著分析考慮與不考慮閘極漏電流，其考慮閘極漏電流會使電容突跳更加嚴重。第一章介紹絕緣體上矽(SOI)的由來與發展趨勢，接著敘述元件縮小所遭遇的困難，引用ITRS的資料描述現今SOI元件的尺寸與未來趨勢。第二章提出部分解離絕緣體上矽N型金氧半之淺槽隔離對窄通道元件對元件影響，由實驗數據分析並討論。第三章為部份解離絕緣體上矽N型金氧半閘極漏電流對本質電容的影響，透過元件二維模擬器的幫助，可以找出PD SOI NMOS電流突增效應對應本質電容之關 係，與閘極漏電流造成電容的影響。第四章為總結與未來工作。 | zh_TW |
| dc.description.abstract | This thesis reports the 2nd order effects of the 65nm PD SOI NMOS device. First, the shallow-trench-isolation-related narrow channel effect on kink effect and the breakdown behavior are analyzed, then the gate tunneling current and the floating-body-effect related capacitance behavior of 65nm PD SOI NMOS device are described. Finally, we make a conclusion and future work. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T01:57:02Z (GMT). No. of bitstreams: 1 ntu-98-R96943086-1.pdf: 5917824 bytes, checksum: 33270c1221e9b56593ce8015ed7f94ca (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | 第一章 導論 1
1.1 元件縮小(Scaling Trends of SOI) 2 1.2 部分解離絕緣體上矽金氧半(PD SOI) 3 1.3 機械張力(Mechanical Stress) 5 1.4 穿隧電流(Tunneling Current) 6 1.5 電容介紹(Capacitance Behavior) 7 1.6 論文結構(Thesis Structure) 8 1.７ 參考文獻(Reference) 9 第二章 奈米級部分解離絕緣體上矽N型金氧半元件之淺槽隔離對於窄通道效應在電流突增與崩潰行為之影響 11 2.1 量測結果(Measurement Results) 12 2.2 討論(Discussion) 18 2.3 結論(Conclusion) 20 2.4 參考文獻(Reference) 21 第三章 考慮閘極漏電流與浮動基體電流突增造成部分解離絕緣體上矽N型金氧半元件之電容影響與分析 23 3.1 電流突增效應(Kink Effect) 24 3.2 元件結構(Device Structure) 25 3.3 直流特性(I-V Curve) 27 3.4 電容行為(Capacitance Behavior) 29 3.5 結論(Conclusion) 40 3.6 參考文獻(Reference) 41 第四章 總結與未來工作 42 Appendix 43 | |
| dc.language.iso | zh-TW | |
| dc.subject | 電容 | zh_TW |
| dc.subject | 機械張力 | zh_TW |
| dc.subject | capacitance | en |
| dc.subject | Mechanical | en |
| dc.title | 60奈米部分解離絕緣體上矽N型金氧半元件二次效應
探討與閘極穿隧電流影響電容分析 | zh_TW |
| dc.title | Second Order Effect of 60nm PD SOI NMOS and Gate
Tunneling Current Related Capacitance Behavior | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 賴飛羆,林吉聰,陳正雄,蔡成宗 | |
| dc.subject.keyword | 機械張力,電容, | zh_TW |
| dc.subject.keyword | Mechanical,capacitance, | en |
| dc.relation.page | 44 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2009-06-26 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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