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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李建模(Chien-Mo Li) | |
dc.contributor.author | Wei-Che Wang | en |
dc.contributor.author | 王偉哲 | zh_TW |
dc.date.accessioned | 2021-06-15T01:42:56Z | - |
dc.date.available | 2011-07-17 | |
dc.date.copyright | 2009-07-17 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-07-13 | |
dc.identifier.citation | [Bardell 87] P.H. Bardell, W.H. McAnney, and J. Savir, Built-in Test for VLSI: Pseudorandom Techniques, John Wiley & Sons, 1987.
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Test Conf., Paper 35.1, 2008. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/43212 | - |
dc.description.abstract | 本論文提出了一個利用列、行,與線性回授移位暫存器的特性來設計未知回應遮蔽的架構,可以有效地壓縮含有很高比例未知回應的測試結果。有別於傳統遮蔽未知回應的技術在壓縮結果進入壓縮器之前就遮蔽未知回應,本論文提出了在壓縮器之後遮蔽未知回應的架構。此提出的架構能非常容易地整合至現有壓縮器,而且進一步提高了整體的壓縮倍率。利用論文中提出的三個有效的機制(整列遮蔽,整行遮蔽,以及線性回授移位暫存器遮蔽機制),此遮蔽未知回應的架構可以使用非常小的線性回授移位暫存器來達到遮蔽全部未知回應的效果。根據實際電路的實驗數據顯示,論文中提出的架構可以提供高於一萬七千倍的輸出壓縮倍率,同時處理高達百分之四十一的未知回應。本論文更進一步提出了分段線性回授移位暫存器的未知回應遮蔽架構,以處理更大的電路以及更多比例的未知回應。由於此架構有非常高的輸出結果壓縮倍率,它非常適合使用於大量平行的測試環境,以大幅降低測試成本。 | zh_TW |
dc.description.abstract | This thesis presents a Row-LFSR-Column (RLC) masking technique that is capable of handling many unknowns in the test responses. Unlike traditional X-masking techniques, which perform unknown masking before the test compactor, the proposed technique masks unknowns after the test compactor. This characteristic makes RLC mask very easy to be applied to existing test response compaction tool and further improves the test response compaction ratio. With three novel mechanism (direct row, direct column, and LFSR column masking), RLC masks all unknowns in the test response using a very short LFSR. Experiment on a real design shows that, RLC mask provides more than 17K times test response compaction for up to 41.8% unknowns. Furthermore, a segmented RLC architecture is presented in order to deal with large industrial designs. By providing a very high test response compaction ratio, the proposed technique enables massive multisite testing to drive down the test cost significantly. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T01:42:56Z (GMT). No. of bitstreams: 1 ntu-98-R96943118-1.pdf: 1000586 bytes, checksum: 33eef06d69b7e94477ed017c069e6f9b (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | 摘要 iv
Abstract v Table of Contents vi List of Figures viii List of Tables x Chapter 1 1 Introduction 1 1.1 Motivation 1 1.2 Proposed Architecture 4 1.3 Contributions 5 1.4 Organization 7 Chapter 2 8 Background 8 2.1 Test Response Compaction 8 2.1.1 Spatial Compaction 8 2.1.2 Temporal Compaction 9 2.1.3 Mixed Spatial and Temporal Compaction 10 2.2 Unknowns in Test Response Compaction 12 2.3 Past Research in Test Response Compaction with Unknowns 14 2.3.1 X-Blocking 14 2.3.2 X-Tolerant 15 2.3.3 X-Masking 21 2.4 Summary and Comparisons 24 Chapter 3 26 Proposed Technique 26 3.1 Hardware Architecture 26 3.2 Three Masking Mechanism 27 3.3 ATPG Flow 31 3.4 RLC Encoding Algorithm 32 3.5 LFSR Seed Computation 35 3.6 RLC Encoding Example 40 Chapter 4 43 Experimental Results 43 4.1 Results of ISCAS89 and ITC99 43 4.2 Results of Industrial Circuits 49 4.3 Comparison with Other Techniques 52 Chapter 5 54 Segmented RLC 54 5.1 Architecture 54 5.2 Experimental Results 57 Chapter 6 60 Summary 60 Reference 61 Appendix 65 | |
dc.language.iso | zh-TW | |
dc.title | 包含未知訊號之測試結果壓縮設計 | zh_TW |
dc.title | Test Response Compaction In The Presence Of Many Unknowns | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 饒建奇,李進福 | |
dc.subject.keyword | 壓縮,未知,測試, | zh_TW |
dc.subject.keyword | compaction,LFSR,test response, | en |
dc.relation.page | 68 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2009-07-13 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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