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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/43212
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dc.contributor.advisor李建模(Chien-Mo Li)
dc.contributor.authorWei-Che Wangen
dc.contributor.author王偉哲zh_TW
dc.date.accessioned2021-06-15T01:42:56Z-
dc.date.available2011-07-17
dc.date.copyright2009-07-17
dc.date.issued2009
dc.date.submitted2009-07-13
dc.identifier.citation[Bardell 87] P.H. Bardell, W.H. McAnney, and J. Savir, Built-in Test for VLSI: Pseudorandom Techniques, John Wiley & Sons, 1987.
[Barnhart 01] Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, and Brion Keller, “OPMISR: The Foundation for Compressed ATPG Vectors,” Proc. IEEE Int. Test Conf., pp. 748-757, 2001.
[Chandra 08] A. Chandra, Y. Kanzawa, R. Kapur and T.W. Williams, “Adapting Scan Compressions to Designs, ” VLSI Design and Test., pp. 309-318, 2008.
[Chao 05] Mango C.-T. Chao, Seongmoon Wang, Srimat T. Chakradhar, and Kwang-Ting Cheng, “ChiYun Compact: A New Test Compaction Technique for Responses with Unknown Values,” Proc. IEEE Int. Conf. on Computer Design., 2005.
[Chao 07] Mango C.-T. Chao, Kwang-Ting Cheng, Seongmoon Wang, and Srimat T. Chakradhar, “A Hybrid Scheme for Compaction Test Responses with Unknow Values,” Proc. IEEE Int. Conf. on Comput.-Aided Design., pp. 513-519., 2007.
[Chen 06] P.-K. Chen, Y.-T. Hsing, and C.-W. Wu, “On feasibility of HOY: A Wireless Test Methodology for VLSI Chips and Wafers,” Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, pp. 243-246, 2006.
[Chickermane 04] Vivek Chickermane, Brian Foutz, and Brion Keller, “Channel Masking Synthesis for Efficient On-Chip Test Compression,” Proc. IEEE Int. Test Conf., pp. 452-461, 2004.
[Garg 08] R. Garg, R. Putman, and N. A. Touba, “Increasing output Compaction in Presence of Unknowns using an X-Canceling MISR with Deterministic Observation,” Proc. IEEE VLSI Test Symp. pp. 35-42, 2008.
[Han 03] Y. Han, Y. Xu, H. Li, X. Li, A. Chandra, “Test Resource Partitioning Base on Efficient Response Compaction for Test Time and Tester Channels Reduction,” Proc. Asian Test Symp., 2003.
[Han 05c] Y. Han, Y. Hu, H. Li, and X. Li, “Theoretic Analysis and Enhanced X-Tolerance of Test Responses Compact Based On Convolutional Code,” Proc. Asian and South Pacific Design Automation Conf., 2005.
[Han 05d] Y. Han, Y. Hu, H. Li, and A. Chandra, “Test Resource Partitioning Based On Efficient Response Compaction for Test Time and Test Channels Reduction,” J. Comput. Sci. Technol., 2005.
[Hilscher 08] Martin Hilscher, Michael Braun, Michael Richter, Andreas Leininger, Michael Gossel, “Accelerated Shift Register for X-tolerant Test Data Compression,” Proc. European Test Conf., pp. 133–139, 2008.
[ITRS 07] International Technology Roadmap for Semiconductors 2007 Update – Test and Test Equipment, Semiconductor Industry Association, 2007.
[Kakade 07] Kakade, J. and Kagaris, D., “Minimization of Linear Dependencies Through the Use of Phase Shifters, ” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.26, no.10, pp.1877-1882, Oct. 2007
[Könemann 91] B. Könemann, “LFSR-Coded Test Patterns for Scan Designs,” Proc. European Test Conf., pp. 237–242, 1991.
[Leininger 07] Andreas Leininger, Martin Fischer, Michael Richter, Michael Braun, and Michael Goessel, “Using Timing Flexibility of Automatic Test Equipment to compliment X-tolerant Test Compression Techniques,” Proc. IEEE Int. Test Conf., Paper 6.3, 2007.
[Mitra 02] S. Mitra and K. S. Kim, “X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction,” Proc. IEEE Int. Test Conf., pp. 311-320, 2002.
[Mrugalski 09] G. Mrugalski, N. Mukherjee, J. Rajski, D. Czysy and J. Tyszer, “Highly X-Tolerant Selective Compaction of Test Responses,” Proc. IEEE VLSI Test Symp. pp. 245-250, 2009.
[Naruse 03] M. Naruse, I. Pomeranz, S. M. Reddy, and S. Kundu, “On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding,” Proc. IEEE Int. Test Conf., pp.1060-1068, 2003.
[Patel 03] J. H. Patel, S. S. Lumetta, and S. M. reddy. “Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns,” Proc. IEEE VLSI Test Symp. pp. 107-112, 2003.
[Rajski 06] J. Rajski, J. Tyszer, G. Mrugalski, W.-T. Cheng, N. Mukherjee, and M. Kassab, “X-Press Compactor for 1000x Reduction of Test Data,” Proc. IEEE Int. Test Conf., Paper 18.1, 2006.
[Sharma 05] M. Sharma and W.-T. Cheng, “X-Filter: Filtering unknowns. from compacted test responses,” Proc. IEEE Int’l Test Conf., pp.1090-1098, 2005.
[Tang 05] H. Tang, C. Wang, J. Ralski, S. M. Reddy, J. Tyszer, and I. Pomeranze, “On Efficient X-Handking Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios,” Proc. Int. Conf. on VLSI Design., pp. 59-64, 2005.
[Touba 07] N. A. Touba, “X-Canceling MISR – An X-Tolerant Methodology for Compacting Output Responses with Unknowns Using a MISR,” Proc. IEEE Int. Test Conf., Paper 6.2, 2007.
[Volkerink 05] E. H. Volkerink, and S. Mitra, “Response Compaction with any Number of Unknowns using a New LFSR Architecture,” Proc. Design Automation Conf., pp. 117-122, 2005.
[Wang 04] L.-T. Wang, X. Wen, H. Furukawa, and F.-S Hsu, “VirtualScan: A New Compressed Scan Technology for Test Cost Reduction,” Proc. IEEE Int. Test Conf., Paper 33.1, 2004.
[Wang 06] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann, July 2006.
[Wang 08a] S. Wang, K. J. Balakrishnan, and W. Wei, “X-Block: An Efficient LFSR Reseeding-based Method to Block Unknowns for Temporal Compactors,” IEEE Trans. Computers, vol. 57, no. 7, pp. 978-989, July 2008.
[Wang 08b] S. Wang, and W. Wei, “An Efficient Unknown Blocking Scheme for Low Control Data Volume and High Observability,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 11, pp. 2039-2052., Nov. 2008.
[Wohl 07] P. Wohl, J. A. Waicukauski, and S. Ramnath, “Fully X-tolerant Combinational Scan Compression,” Proc. IEEE Int. Test Conf., Paper 6.1, 2007.
[Wohl 08] P. Wohl, J. A. Waicukauski, and F. Neuveux, “Increasing Scan Compression by Using X-chains,” Proc. IEEE Int. Test Conf., Paper 35.1, 2008.
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/43212-
dc.description.abstract本論文提出了一個利用列、行,與線性回授移位暫存器的特性來設計未知回應遮蔽的架構,可以有效地壓縮含有很高比例未知回應的測試結果。有別於傳統遮蔽未知回應的技術在壓縮結果進入壓縮器之前就遮蔽未知回應,本論文提出了在壓縮器之後遮蔽未知回應的架構。此提出的架構能非常容易地整合至現有壓縮器,而且進一步提高了整體的壓縮倍率。利用論文中提出的三個有效的機制(整列遮蔽,整行遮蔽,以及線性回授移位暫存器遮蔽機制),此遮蔽未知回應的架構可以使用非常小的線性回授移位暫存器來達到遮蔽全部未知回應的效果。根據實際電路的實驗數據顯示,論文中提出的架構可以提供高於一萬七千倍的輸出壓縮倍率,同時處理高達百分之四十一的未知回應。本論文更進一步提出了分段線性回授移位暫存器的未知回應遮蔽架構,以處理更大的電路以及更多比例的未知回應。由於此架構有非常高的輸出結果壓縮倍率,它非常適合使用於大量平行的測試環境,以大幅降低測試成本。zh_TW
dc.description.abstractThis thesis presents a Row-LFSR-Column (RLC) masking technique that is capable of handling many unknowns in the test responses. Unlike traditional X-masking techniques, which perform unknown masking before the test compactor, the proposed technique masks unknowns after the test compactor. This characteristic makes RLC mask very easy to be applied to existing test response compaction tool and further improves the test response compaction ratio. With three novel mechanism (direct row, direct column, and LFSR column masking), RLC masks all unknowns in the test response using a very short LFSR. Experiment on a real design shows that, RLC mask provides more than 17K times test response compaction for up to 41.8% unknowns. Furthermore, a segmented RLC architecture is presented in order to deal with large industrial designs. By providing a very high test response compaction ratio, the proposed technique enables massive multisite testing to drive down the test cost significantly.en
dc.description.provenanceMade available in DSpace on 2021-06-15T01:42:56Z (GMT). No. of bitstreams: 1
ntu-98-R96943118-1.pdf: 1000586 bytes, checksum: 33eef06d69b7e94477ed017c069e6f9b (MD5)
Previous issue date: 2009
en
dc.description.tableofcontents摘要 iv
Abstract v
Table of Contents vi
List of Figures viii
List of Tables x
Chapter 1 1
Introduction 1
1.1 Motivation 1
1.2 Proposed Architecture 4
1.3 Contributions 5
1.4 Organization 7
Chapter 2 8
Background 8
2.1 Test Response Compaction 8
2.1.1 Spatial Compaction 8
2.1.2 Temporal Compaction 9
2.1.3 Mixed Spatial and Temporal Compaction 10
2.2 Unknowns in Test Response Compaction 12
2.3 Past Research in Test Response Compaction with Unknowns 14
2.3.1 X-Blocking 14
2.3.2 X-Tolerant 15
2.3.3 X-Masking 21
2.4 Summary and Comparisons 24
Chapter 3 26
Proposed Technique 26
3.1 Hardware Architecture 26
3.2 Three Masking Mechanism 27
3.3 ATPG Flow 31
3.4 RLC Encoding Algorithm 32
3.5 LFSR Seed Computation 35
3.6 RLC Encoding Example 40
Chapter 4 43
Experimental Results 43
4.1 Results of ISCAS89 and ITC99 43
4.2 Results of Industrial Circuits 49
4.3 Comparison with Other Techniques 52
Chapter 5 54
Segmented RLC 54
5.1 Architecture 54
5.2 Experimental Results 57
Chapter 6 60
Summary 60
Reference 61
Appendix 65
dc.language.isozh-TW
dc.subject測試zh_TW
dc.subject壓縮zh_TW
dc.subject未知zh_TW
dc.subjectcompactionen
dc.subjectLFSRen
dc.subjecttest responseen
dc.title包含未知訊號之測試結果壓縮設計zh_TW
dc.titleTest Response Compaction In The Presence Of Many Unknownsen
dc.typeThesis
dc.date.schoolyear97-2
dc.description.degree碩士
dc.contributor.oralexamcommittee饒建奇,李進福
dc.subject.keyword壓縮,未知,測試,zh_TW
dc.subject.keywordcompaction,LFSR,test response,en
dc.relation.page68
dc.rights.note有償授權
dc.date.accepted2009-07-13
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept電子工程學研究所zh_TW
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