可重組面積優化渦輪解碼器之演算法與積體電路設計

Abstract

隨著多媒體服務的快速成長，為了取得在雜訊通道中可靠的資料傳輸，渦輪碼（convolutional turbo code）已經廣泛地應用在無線通訊系統中，並且成為這些系統中前饋式錯誤更正（forward error correction）機制之一。此外，多數前瞻的無限通訊標準會採用不同的渦輪碼機制，例如：單二元（single-binary）渦輪碼與雙二元（double-binary）渦輪碼，並且伴隨著各式各樣的框架大小與吞吐率。因此，一個專為應用於多標準渦輪解碼的可重組化且面積優畫的硬體設計是相當重要的。 適用於高吞吐量渦輪解碼，以視窗解碼（window-based decoding）為基礎、平行且可量化的最大事後機率演算法（maximum a posteriori algorithm，MAP）廣泛地使用於處理任何框架大小的解碼。本論文第一部份提出三種將平行視窗（parallel-window，PW)）與綜合視窗（hybrid-window，HW）以面積優化結合的MAP解碼，可以在平行視窗MAP解碼與綜合視窗MAP解碼間切換。為了驗證所提出的概念，一個單位元與雙位元雙模式2PW-1HW MAP處理器以0.13 μm CMOS製程實現在一顆面積1.28 mm2的晶片上。這顆原型晶片在操作頻率125 MHz下可以達到500 Mbps的吞吐率且解碼面積效率為3.13 bits/mm2。適用於多標準系統，五顆雙模式2PW-1HW MAP處理器即可達到WiMAX與LTE渦輪解碼所預期的吞吐量。 由於渦輪解碼的疊代運算造成了解碼時很高的記憶體功率耗損。本論文第二部份提出了低成本低功率的追回式（Traceback）最大機率演算法來降低狀態記憶體快取（state metrics cache）所耗損的功率。針對雙二元最大機率演算法，以二乘二為基底和以四為基底的追回式架構提供了功率消耗與操作頻率的選擇架構。這兩個架構可以為雙位元渦輪解碼器取得約7%的功率下降。一個高吞吐量採用二乘二為基底追回式架構的12模式WiMAX渦輪解碼器以0.13 μm CMOS製程實現在一顆面積7.16 mm2的晶片上。這顆原型晶片在操作頻率100 MHz下可以達到115.4 Mbps的吞吐率且解碼面積效率為0.18 bits/mm2、能源效率為0.43 nJ/bit per iteration。 本論文第三部份提出一個可以同時支援單位元和雙位元渦輪解碼的雙模（單位元�雙位元）以四為基底的最大機率演算法。這個雙模最大機率演算法的運算模組與存取單元在以達到高面積使用率的考量下被設計出來。與一個沒有硬體共用的單位元和雙位元最大機率演算法處理器來做比較，所提出的雙模最大機率演算法處理器可以減少約45%的面積。為了驗證所提出的概念，一個高吞吐量採用二乘二為基底追回式架構的35模式WiMAX/LTE渦輪解碼器以90 nm CMOS製程實現在一顆面積3.38 mm2的晶片上。這顆原型晶片在操作頻率164 MHz下可以達到241.2 Mbps的吞吐率且解碼面積效率為0.43 bits/mm2。 總結本論文所提出上述三種面積優畫迴旋渦輪解碼的設計方式，皆可同時應用在任何前瞻通訊系統的渦輪碼中，本論文並針對目前廣泛使用的通訊標準，以三顆不同應用的原型晶片來驗證所提出這三種面積優畫迴旋渦輪解碼的設計方法。

With the rapid growth of multimedia services, convolutional turbo codes (CTCs) have been widely adopted as one of forward error correcting (FEC) schemes for wireless communications to have a reliable transmission over noisy channels. Most of advanced wireless standards have adopted distinct CTC schemes, such as single-binary (SB) CTC or double-binary (DB) CTC, with various block sizes and throughput rates. Thus, a reconfigurable and area-efficient dedicated hardware design for multistandard CTC decoding is necessary. To perform the alternative parallel-window (PW) and hybrid-window (HW) maximum a posteriori algorithm (MAP) decoding, three area-efficient combinations of PW and HW MAP decoding are proposed in this dissertation. To verify the proposed approach, a 1.28 mm2 dual-mode (SB/DB) 2PW-1HW MAP processor is implemented in 0.13 μm CMOS process. The prototyping chip achieves a maximum throughput rate of 500 Mbps at 125 MHz with an area efficiency of 3.13 bits/mm2. For the multistandard systems, the expected throughput rates of the WiMAX and LTE CTC schemes is achieved by using five dual-mode 2PW-1HW MAP processors. The iterative decoding of CTC has a large memory power consumption. To reduce the power consumption of the state metrics cache (SMC), low-cost and low-power memory-reduced traceback MAP decoding is proposed. For double-binary (DB) MAP decoding, radix-2x2 and radix-4 traceback structures are introduced to provide a tradeoff between power consumption and operating frequency. These two traceback structures achieve an around 7% power reduction of the DB MAP decoders. A high-throughput 12-mode WiMAX CTC decoder applying the proposed radix-2x2 traceback structure is implemented by using a 0.13 μm CMOS process in a core area of 7.16 mm2. Based on post-layout simulation results, the proposed decoder achieves a maximum throughput rate of 115.4 Mbps at 100 MHz with an area efficiency of 0.18 bits/mm2 and an energy efficiency of 0.43 nJ/bit per iteration. Finally, dual-mode (SB/DB) radix-4 MAP decoding is proposed. The computational modules and storages of the dual-mode (SB/DB) MAP decoding are designed to achieve a high area utilization. The proposed dual-mode MAP decoding can achieve around 45% silicon area reductions compared with the hardware non-shared radix-4 SB MAP and radix-4 DB MAP decoding. To verify the proposed approaches, a 3.38 mm2 35-mode WiMAX/LTE CTC decoder is implemented in 90 nm CMOS process. The prototyping chip achieves a maximum throughput rate of 241.2 Mbps at 164 MHz with an area efficiency of 0.43 bits/mm2. To the best of our knowledge, the prototyping decoder chip is the first CTC decoder to meet the throughput rate requirements of WiMAX and LTE CTC schemes. In summary, the proposed three designs of the area-efficient CTC decoding are applied to the CTC schemes of advanced communication systems. To verify the proposed designs for the prevalent communication standards, three prototyping implementations of CTC decoding are presented in this dissertation.