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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/43104完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳秋麟(Chern-Lin Chen) | |
| dc.contributor.author | Po-Chun Huang | en |
| dc.contributor.author | 黃柏鈞 | zh_TW |
| dc.date.accessioned | 2021-06-15T01:37:07Z | - |
| dc.date.available | 2011-08-11 | |
| dc.date.copyright | 2009-08-11 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-07-16 | |
| dc.identifier.citation | [1] Limits for Harmonic Current Emissions, IEC/EN61000-3-2, 1995.
[2] B. Gilbert, “A precise four-quadrant multiplier with subnanosecond response,” IEEE J. Solid-State Circuits, vol. SC-3, pp. 353–365, Dec. 1968. [3] G. Han and E. S´anchez-Sinencio, “CMOS transconductance multipliers: a tutorial,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 12, pp.1550-1563, Dec. 1998. [4] G.A. Hadgis and P.R. Mukund, “A novel CMOS monolithic analog multiplier with wide input dynamic range,” in Proc. Int. Conf. VLSI Design, New Delhi, India, 1995, pp. 310-314. [5] 宋自恆，林慶仁， “功率因數修正電路之原理與常用元件規格, ” 新電子科技雜誌，第217期，2004年4月號。 [6] “L6561, enhanced transition-mode power factor corrector,” AN966 , www.st.com. [7] 'L6562 power factor corrector,' Datasheet, www.st.com. [8] 'Design of fixed-off-time-controlled PFC pre-regulators with the L6562,' AN1792, www.st.com. [9] A. L. Coban and P. E. Allen, “Low-voltage CMOS transconductance cell based on parallel operation of triode and saturation transconductors,” Electron. Lett., vol. 30, pp. 1124–1126, July 1994. [10] G. Moon, M. E. Zaghloul, and R. W. Newcomb, 'An enhancement-mode MOS voltage-controlled linear resistor with large dynamic range,' IEEE Trans. Circuits Syst., vol. 37, no. 10, pp. 1284 – 1288, Oct. 1990. [11] Z. Wang, 'Automatic VT extractors based on an n x n2 MOS transistor array and their application,' IEEE J. of Solid-State Circuits, vol. 27, no. 9, pp. 1277-1285, Sep. 1992. [12] U. Cilingiroglu and S.K. Hoon, 'An accurate self-bias threshold voltage extractor using differential difference feedback amplifier,' in Proc. IEEE Int. Symp. Circuit and Systems, Geneva, Switzerland, 2000, pp. V-209-V-212. [13] E. Sackinger and W. Guggenbuhl, 'A versatile building block: the CMOS differential difference amplifier,' IEEE J. Solid-State Circuits, vol.22, pp. 287-294, Apr. 1987. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/43104 | - |
| dc.description.abstract | 近年來因諧波失真問題被重視，為了符合各國所訂定的標準，功率因數校正電路已為電源供應器重要的一部分；在現行主動式功率因數校正電路架構中，類比乘法器為控制電路中的核心。本文主要探討應用於功率校正電路之類比乘法器，提出透過將輸入電壓位準向上平移一個臨界電壓，改良利用兩MOS並聯，一個操作在線性區，一個操作在飽和區，所形成的線性可變電阻，運用於非反向放大器，透過輸入改變可變電阻大小，改變非反向放大器閉迴路增益達到乘法器之功能；並將邊界導通模式升壓功率因數校正電路的控制迴路做出，將所改良的類比乘法器應用於其中，將電路結果用Hspice模擬出，以驗證所提出的類比乘法器適合應用於功率校正電路。 | zh_TW |
| dc.description.abstract | In recent years, harmonic distortion problem has been emphasized. To achieve the standards which were made by each country, power factor correctors have played an important role in switching power supplies. In current architecture of active power factor corrector, input current is controlled by input voltage which multiplies feedback control signal to become sinusoidal wave; hence analog multipliers are the heart of the control circuits. This thesis mainly discusses on an analog multiplier which can be applied to power factor corrector, and purposes a method by shifting input voltage up one threshold voltage, improving the analog multiplier using linear variable resistor applies in non-inverting amplifier. The linear variable resistor is composed of two MOS in parallel. One is operated in linear region, and the other is operated in saturation region. The value of linear variable resistance will change by input; therefore change the gain of non-inverting amplifier to realize multiplier. In this thesis, a complete boundary conduction mode boost PFC circuit is built with the proposed multiplier. Finally, simulation outcomes of Hspice verify that the purposed multiplier can be used for PFC circuit. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T01:37:07Z (GMT). No. of bitstreams: 1 ntu-98-R96943017-1.pdf: 951621 bytes, checksum: 7b5e480a3752fd0124f79cf6b04abb12 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | 第一章 序論 1
1.1 研究背景與動機 1 1.2 論文架構 3 第二章 功率因數校正 4 2.1 功率因數校正原理 4 2.2 升壓功率因數校正電路系統 6 第三章 類比乘法器架構 9 3.1 一般類比乘法器原理 9 3.2 可變線性電阻乘法器 16 第四章 改良可變線性電阻乘法器 18 4.1 改良動機 18 4.2 改良電路架構 19 4.3 臨界電壓取出電路 23 4.4 電路不理想效應 28 第五章 邊界導通模式升壓功率因數校正電路架構 29 5.1 電路整體架構 29 5.2 輸出回授放大器 32 5.3 電壓比較器 33 5.4 零電流偵測電路 34 5.5 SR閂鎖與閘極驅動電路 37 第六章 模擬結果 40 6.1 改良線性電阻類比乘法器模擬結果 40 6.2 邊界導通模式升壓功率因數校正電路模擬結果 45 第七章 總結 48 7.1 總結 48 7.2 未來展望 48 參考文獻 49 | |
| dc.language.iso | zh-TW | |
| dc.title | 應用於邊界導通模式升壓功率因數校正電路之類比乘法器 | zh_TW |
| dc.title | Analog Multiplier for Boundary Conduction Mode Boost Power Factor Correction Circuit | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 廖聰明(Chang-Ming Liaw),劉添華(Tian-Hua Liu),梁適安,陳耀銘(Yaow-Ming Chen) | |
| dc.subject.keyword | 功率因數校正電路,類比乘法器, | zh_TW |
| dc.subject.keyword | Power factor correction circuit,cmos analog multiplier, | en |
| dc.relation.page | 50 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2009-07-16 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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