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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃鐘揚(Chung-Yang Huang) | |
dc.contributor.author | Chin-Chia Nien | en |
dc.contributor.author | 粘敬佳 | zh_TW |
dc.date.accessioned | 2021-06-15T01:30:56Z | - |
dc.date.available | 2009-07-23 | |
dc.date.copyright | 2009-07-23 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-07-20 | |
dc.identifier.citation | [1] David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda, “Slope Propagation in Static Timing Analysis,” In the Proceedings of International Conference on Computer-Aided Design, 2000, page. 338-343.
[2] D. Blaauw, K. Chopra, A. Srivastava, and L. Scheffer, “Statistical Timing Analysis: From Basic Principles to State of the Art,” In Proceedings of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, 2008, page. 589-607. [3] S. Borkar, T. Karnik, and Vivek De, “Design and reliability challenges in nanometer technologies,” In Proceedings of Design Automation Conference, 2004, page. 75. [4] S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, “Parameter variations and impact on circuits and microarchitecture,” In Proceedings of Design Automation Conference, 2003, page. 338-342. [5] A. Mutlu and M. Rahman, “Statistical methods for the estimation of process variation effects on circuit operation,” In Proceedings of IEEE Transactions on Electronics Packaging Manufacturing, vol. 28, 2005, page. 364-375. [6] Lin Xie, A. Davoodi, Jun Zhang, and Tai-Hsuan Wu, “Adjustment-based modeling for Statistical Static Timing Analysis with high dimension of variability,”. In the Proceedings of International Conference on Computer-Aided Design, 2008, page. 181-184. [7] S. Onaissi and F. Najm, “A Linear-Time Approach for Static Timing Analysis Covering All Process Corners,” In Proceedings of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, 2008, page. 1291-1304. [8] K. Heloue and F. Najm, “Parameterized timing analysis with general delay models and arbitrary variation sources,” In Proceedings of Design Automation Conference, 2008, page. 403-408. [9] I. Keller, King Ho Tarn, and V. Kariat, “Challenges in gate level modeling for delay and SI at 65nm and below,” In Proceedings of Design Automation Conference, 2008, page. 468-473. [10] L. Silva, Miguel Silveira L z, and J. Phillips, “Efficient Computation of the Worst-Delay Corner,”In Proceedings of Design, automation and test in Europe, 2007, page. 1-6. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42970 | - |
dc.description.abstract | 在本論文中,我們提出了一個考慮多重邊界與操作模式之靜態時序分析引擎。它能在不同的大電路中有效率地計算出許多製程邊界中最大的延遲。我們關鍵的貢獻在於:(一)路徑模式與參數模式的縝密結合,使得此引擎在不同的電路下都是很健全的。(二)增強的搜尋空間刪除技巧。(三)簡易而有效率地計算出關鍵路徑延遲界限,大大地加強了起始搜尋空間刪除的能力。(四)延伸到保持時間的確認。我們的實驗結果顯示出在不同參數數量與不同電路下,我們的引擎都比以往的考慮多重編界與操作模式之靜態時序分析方法還要傑出。 | zh_TW |
dc.description.abstract | In this thesis, we proposed a unified Multi-Corner Multi-Mode (MCMM) static timing analysis (STA) engine that can efficiently compute the worst-case delay of the process corners in various very large scaled circuits. Our key contributions include: (1) a seamless integration of the path- and parameter-based branch-and-bound algorithms so that the engine is very robust for different kinds of circuits, (2) an improved search space pruning technique, (3) a simple yet efficient critical path delay bound for the initial search space pruning, and (4) an extension to the hold-time check. Our experimental results show that our engine can significantly outperform the prior MCMM STA approaches in various benchmark circuits with different number of process parameters. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T01:30:56Z (GMT). No. of bitstreams: 1 ntu-98-R95921029-1.pdf: 262048 bytes, checksum: 04c6ff93d9c024ed26d4260a0605aa70 (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | 誌謝 I
摘要 II Abstract III Table of Contents IV List of Figures VII List of Tables VIII Chapter 1 Introduction 1 1.1 Static Timing Analysis 1 1.2 Taxonomy of the Process Variations 3 1.3 Variation-Aware Static Timing Analysis 4 1.4 Statistical Static Timing Analysis 5 1.5 Multi-Corner Multi-Mode Static Timing Analysis 5 1.6 Linear-Time Approximation Approach for MCMM STA 6 1.7 Exact Delay Upper-Bound Computation Approach for MCMM STA 7 1.8 Contributions of this Thesis 7 Chapter 2 Previous Works on MCMM STA 9 2.1 Linear Modeling of Process Variations 10 2.2 Approximate MCMM STA 12 2.3 Exact MCMM STA 15 Chapter 3 MCMM STA Algorithms 18 3.1 Linear Time Approximation Approach 18 3.2 Exhaustive Method for the MCMM Timing Analysis 22 3.3 Dynamic Pruning Method in Exact MCMM STA Algorithms 24 Chapter 4 The Unified MCMM STA Engine 26 4.1 Overview of the Unified Engine 26 4.2 Improved Path-Based BNB 29 4.3 Improved Parameter-Based BNB 30 4.4 Candidate Critical Path Delay for Initial Search Space Pruning 34 4.5 Extension to Hold Time Check 35 Chapter 5 Implementation 36 5.1 Data Structure 36 5.2 Input Format 38 Chapter 6 Experimental Results 40 6.1 Improved Path-Based BNB 41 6.2 Improved Parameter-Based BNB 42 6.3 Robustness of Our Unified Engine 43 6.4 The Range of Process Variation 44 6.5 Extension to Hold Time Check 45 Chapter 7 Conclusions 46 Reference 47 | |
dc.language.iso | zh-TW | |
dc.title | 考慮多重邊界與操作模式之靜態時序分析引擎 | zh_TW |
dc.title | A Unified Multi-Corner Multi-Mode Static Timing Analysis Engine | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 李建模(Chien-Mo Li),王信博(Hsin-Po Wang) | |
dc.subject.keyword | 考量變動的靜態時序分析,多重邊界與操作模式,分枝與跳躍,仿射函數,製程變動, | zh_TW |
dc.subject.keyword | variation-aware timing analysis,multi-corner multi-mode,branch-and-bound,affine function,process variations, | en |
dc.relation.page | 48 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2009-07-21 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
顯示於系所單位: | 電機工程學系 |
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