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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 賴飛羆(Feipei Lai) | |
dc.contributor.author | Yu-An Li | en |
dc.contributor.author | 李育安 | zh_TW |
dc.date.accessioned | 2021-06-15T01:18:22Z | - |
dc.date.available | 2011-07-30 | |
dc.date.copyright | 2009-07-30 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-07-27 | |
dc.identifier.citation | [1]J. C. Hu, and R. Marculescu, “DyAD - smart routing for networks-on-chip,” in Proc. of Design Automation Conference, pp. 260–263, 2004.
[2]L. Benini and G. De Micheli, “Networks on chips: a new SoC paradigm,” Computer, vol. 35, pp. 70-78, 2002. [3]W. J. Dally and B. Towles, “Route packets, not wires: on-chip interconnection networks,” Proceedings. Design Automation Conference, pp. 684-689, 2001. [4]A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. Öberg, M. Millberg, D. Lindquist, “Network on a Chip: An architecture for billion transistor era”, NORCHIP 2000, Turku, Finland, November 2000. [5]S. Kumar, A. Jantsch, J. P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani, “A network on chip architecture and design methodology,” Proceedings. ISVLSI, pp. 105-112, 2002. [6]W. J. Dally and B. Towles. Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004. [7]P. Mohapatra, “Wormhole Routing Techniques for Directly Connected Multicomputer Systems,” ACM Computing Surveys, vol. 30, no. 8, pp. 374-410, September 1998. [8]S. Kumar et. al., “A Network on Chip Architecture and Design Methodology”, accepted for publication in IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, Pennsylvania, USA, April 25-26, 2002. [9]A. Adriahantenaina et al., “SPIN: a Scalable, Packet Switched, On-chip Micro-network,” Proc. Design and Test in Europe, Mar. 2003. [10]M. Mirza-Aghatabar, S. Koohi, S. Hessabi, and Massoud Pedram, “An empirical investigation of Mesh and Torus NoC topologies under different routing algorithms and traffic models,” in Proceedings of the 10th IEEE Euromicro Conference on Digital System Design, pp. 19-26, Luebeck-Germany, 29-31 August, 2007. [11]F. Karim, A. Nguyen, and S. Dey, “An interconnect architecture for networking systems on chips,” Micro, IEEE, vol. 22, pp. 36-45, 2002. [12]M. Hosseinabady, M. R. Kakoee, J. Mathew, and D. K. Pradhan, “Reliable Network-on-Chip Based on Generalized de Bruijn Graph,” IEEE International High Level Design Validation and Test Workshop, pp. 3-10, 2007. [13]G.-M. Chiu, “The Odd-Even Turn Model for Adaptive Routing,” IEEE Trans. Parallel and Distributed Systems, vol. 11, no. 7, pp. 729-738, July 2000. [14]M. Daneshtalab , A. Pedram , M. H. Neishaburi , M. Riazati , A. Afzali-Kusha , S. Mohammadi, “Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections,” Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems, p.546-550, January 06-10, 2007. [15]D. Wu, B.M. Al-Hashimi, and M.T. Schmitz, “Improving Routing Efficiency for Network-on-Chip through Contention-Aware Input Selection,” Proc. Asia and South Pacific Design Automation Conf., pp. 36-41, 2006. [16]G. Ascia, V. Catania, M. Palesi, D. Patti, “Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip”, Proc. IEEE Transactions on Computers, 57(6), pp. 809-820, June 2008. [17]M. Daneshtalab, A. Afzali-Kusha, S. Mohammadi, “Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output Selections”, in Proceedings of 20th VLSID, IEEE Press, India, Jan 2007. [18]P. Lotfi Kamran, Z. Navabi, C. Lucas, and M. Daneshtalab, “BARP: A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs”. The 11th DATE Conference and Exhibition: Design Automation and Test in Europe, 10- 14 March, 2008. [19]P. Gratz, B. Grot, and S. W. Keckler, “Regional congestion awareness for load balance in networks-on-chip,” in Proceedings of the 14th IEEE International Symposium on High-Performance Computer Architecture, February 2008. [20]Y. C. Lan, M. Chen, A. Su, Y. H. Hu, and S. J. Chen, “Flow Maximization for NoC Routing Algorithms,” IEEE Computer Society Annul Symposium on VLSI, pp. 335-340, Montpellier, France, Apr. 2008. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42636 | - |
dc.description.abstract | 隨著晶片製程技術的進步,現今一個晶片已經可以容納大量的電晶體,也因此讓晶片系統(system-on-a-chip)的設計者能將大量的矽智產(intellectual property)置於同一晶片之中。然而,矽智產之間訊息的交換,將成為晶片系統中的一個新的挑戰。為了解決各個矽智產之間的溝通問題,近年來晶片網路(Network-on-a-chip)的架構被提出來,並且擁有良好的延展度以及可靠度的晶片網路上的通訊方式。較高效能的傳輸設計已經變成晶片網路中一個重要的議題。在本篇論文當中,以二維網格晶片網路為基礎,我們提出了一個低面積成本並且減少封包間在輸出埠上的競爭。藉由計算路由選擇上擁塞的機率,我們可以為輸入埠緩衝區選擇一個適合的輸出埠並且可改善晶片網路上傳輸效能。 | zh_TW |
dc.description.abstract | With the advance of the semiconductor technology, a huge number of transistors are available on a single chip. This advance allows System-on-chip (SoC) designers to put a lot of intellectual property (IP) blocks in a chip. However, the inter-communication between IP cores becomes main challenge of SoC design. In order to overcome the problem, Network-on-chip (NoC) has been proposed to provide a scalable and reliable on-chip infrastructure in recent years. The high performance design is one of the most important issues to Network-on-chip design and the implementation of scalable communication structures. In this thesis, we propose a Single Router Output Port Selection Mechanism (SROPS) for reducing the packets contention for output ports in a 2D mesh NoC router. By calculating the congestion probability of routing selection in a router, SROPS can choose an appropriate output port for the incoming packets. Experiments show that SROPS, when compared with oe-fixed mechanism, improve the saturation point by 68.97% at the scarification of area increase by 2.3%. Also, among others proposed mechanisms (e.g., BL, turn1, turn), this proposed one increase the saturation point performance by 27.15%, 20.82%, and 19.72% respectively. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T01:18:22Z (GMT). No. of bitstreams: 1 ntu-98-R96944019-1.pdf: 1534897 bytes, checksum: c44e84860714a421b9a5b5236f329896 (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 中文摘要 iii Abstract iv Contents v List of Figures vii List of Tables ix Chapter 1 Introduction 1 1.1 Concept of NoC 1 1.2 Basic NoC architecture 2 1.3 Thesis organization 3 Chapter 2 Background and Related Work 4 2.1 NoC Topology 4 2.1.1 Mesh Topology 4 2.1.2 Torus Topology 5 2.1.3 Tree Topology 6 2.1.4 Octagon [11] 6 2.1.5 De Bruijn Graph [12] 7 2.2 Switching Techniques 8 2.2.1 Communication Unit [6] 8 2.2.2 Store and Forward (SAF) Switching 9 2.2.3 Virtual Cut Through (VCT) Switching 10 2.2.4 Wormhole Switching [7] 10 2.3 NoC Routing 11 2.3.1 Classification of Routing 11 2.3.2 Routing Algorithm 12 2.4 Typical Router in Network on Chip 14 2.5 Related Work 15 Chapter 3 Proposed Method for Output Port Selection 17 3.1Motivation 17 3.2 Problem formulation 18 3.3 Proposed output port selection mechanism 20 3.3.1 Probability of Congestion 21 3.3.2 Single Router Output Port Selection Mechanism (SROPS) 30 Chapter 4 Experiment Result 35 4.1 Simulation environment 35 4.2 Traffic scenarios 36 4.3 Evaluation Metrics 37 4.4 Experiment Result 38 Chapter 5 Conclusion 44 Reference 45 | |
dc.language.iso | en | |
dc.title | 在網格晶片網路上一種動態調適路由有效率的輸出埠選擇方法 | zh_TW |
dc.title | An Efficient Output Port Selecting Method for Adaptive Routing in Mesh-based Network-on-chip | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 張延任,尚榮基,黃國軒,林振群 | |
dc.subject.keyword | 晶片網路,晶片系統,網格,效能,選擇策略, | zh_TW |
dc.subject.keyword | Network-on-chip,System-on-chip,Mesh,Performance,Selection strategy, | en |
dc.relation.page | 47 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2009-07-27 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊網路與多媒體研究所 | zh_TW |
顯示於系所單位: | 資訊網路與多媒體研究所 |
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