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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 顧孟愷 | |
dc.contributor.author | Yi-Ting Liu | en |
dc.contributor.author | 劉奕廷 | zh_TW |
dc.date.accessioned | 2021-06-15T01:15:00Z | - |
dc.date.available | 2012-07-30 | |
dc.date.copyright | 2009-07-30 | |
dc.date.issued | 2009 | |
dc.date.submitted | 2009-07-28 | |
dc.identifier.citation | [1] R.G. Gallager, “Low-Density Parity-Check Codes,” IEEE Transactions on Information Theory, vol. 8, pp. 21-28, Jan. 1962.
[2] D. MacKay and R. Neal, “Good codes based on very sparse matrices,” in Cryptography and Coding, 5th IMA Conf., pp. 100-111, Springer, 1995. [3] High Throughput Extension to the 802.11 Standard, IEEE Working Draft Proposed Standard 802.11n, 2007. [4] IEEE std. 802.16e-2005, “IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems,” Feb. 28th, 2006. [5] Digital Video Broadcasting (DVB) Second Generation Framing Structure for Broadband Satellite Applications, ETSI Std. EN 302 307 v1.1.1, 2005. [6] R. Tanner, “A Recursive Approach to Low Complexity Codes”, IEEE Trans. Information Theory, pp. 533-547, Sep. 1981. [7] H. Zhong and T. Zhang, “Design of VLSI Implementation LDPC Codes,” in Proceeding IEEE 58th Vehicular Technology Conference, vol. 1, pp. 670-673, Oct. 2003. [8] J. Chen, R. Tanner, J. Zhang, and M. Fossorier, “Construction of Irregular LDPC Codes by Quasi-Cyclic Extension,' IEEE Transactions on Information Theory, vol. 53, no. 4, pp. 1479-1483, 2007. [9] S. Lin and D. Costello, Error Control Coding: Fundamentals and Applications. Prentice-Hall, 1983. [10] F. Kschischang, B. Frey, and H. Loeliger, “Factor graphs and the sum-product algorithm,' IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 498{519, 2001. [11] S.-Y. Chung, G. D. Forney, Jr., T. J. Richardson, and R. Urbanke, “On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit,” IEEE Communications Letters, vol. 5, pp. 58-60, Feb. 2001. [12] L. Ping and W. K. Leung, “Decoding low density parity check codes with finite quantization bits,” IEEE Communications Letters, vol. 4, pp. 62-64, Feb. 2000. [13] M. Forssorier, M. Milhaljevic and H. Imai, “Reduced Complexity Iterative Decoding of Low Density Parity Check Codes Based on Belief Propagation,” IEEE Transactions on Communications, pp. 673-680, May 1999. [14] J. Heo, “Analysis of Scaling Soft Information on Low Density Parity Check Code,” Electronics Letters, vol. 39, pp. 219-221, Jan. 2003. [15] D. Hocevar, “A reduced complexity decoder architecture via layered decoding of LDPC codes,” in Proceeding Signal Processing Systems SIPS 2004, pages 107-112, Oct. 2004. [16] E. Sharon, S. Litsyn and J. Goldberger, “An Efficient Message-Passing Scheduling for LDPC Decoding,” in Proceeding 23rd IEEE Convention in Tel-Aviv, pp. 223-226, Sep. 2004. [17] A. I. Vila Casado, M. Griot and R. Wesel, “Informed Dynamic Scheduling for Belief-Propagation Decoding of LDPC codes,” in Proceeding IEEE International Conference on Communications 2007, pp. 932-937, June 2007. [18] A. I. Vila Casado, M. Griot and R. Wesel, “Improving LDPC Decoders via Informed Dynamic Scheduling,” in Proceeding IEEE Information Theory Workshop 2007, pp. 208-213, Sept. 2007. [19] G. Elidan, I. McGraw and D. Koller, “Residual belief propagation: informed scheduling for asynchronous message passing,” in Proceeding 22nd Conference on Uncertainty in Artificial Intelligence, MIT, Cambridge, MA, July 2006. [20] J.-H Kim, M.-Y. Nam and H.-Y Song, “Variable-to-check residual belief propagation for LDPC codes,” IEEE Electronics Letters, Vol. 45, No. 2, January 2009. [21] Saejoon Kim, Karam Ko, Jun Heo and Ji-Hwan Kim, “Two-Staged Informed Dynamic Scheduling for Sequential Belief Propagation Decoding of LDPC Codes,” IEEE Communications Letters, Vol. 13, No. 3, March 2009. [22] T. Richardson, “Error floors of LDPC codes,” in Proceeding. 41st Annual Allerton Conf. on Comm., 2003. [23] A. J. Blanksby and C. J. Howland, “A 690-mW 1-Gb/s 1024-b, Rate-1/2 Low-Density Parity-Check Code Decoder,” IEEE Journal of Solid-State Circuit, Vol. 37, No. 2, Mar. 2002. [24] Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, and An-Yeu (Andy) Wu, “An 8.29 mm2 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 μm CMOS Process,” IEEE Journal of Solid-State Circuit, Vol. 43, No. 3, Mar. 2008. [25] Abhiram Prabhakar, and Krishna Narayanan, “A Memory Efficient Serial LDPC Decoder Architecture,” in IEEE International Conference on Acoustic, Speech, and Signal Processing, Vol.5, pp. v/41 - v/44, Mar. 2005. [26] XtremeDSP Development Platform - Virtex-5 FPGA ML506 Edition. Xilinx Corporation, CA. [Online]. Available: http://www.xilinx.com/products/devkits/ HW-V5-ML506-UNI-G.htm [27] ISE Design Suite: Logic Edition. Xilinx Corporation, CA. [Online]. Available: http://www.xilinx.com/tools/logic.htm | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42502 | - |
dc.description.abstract | 在這篇論文,我們提出了基於一種先進動態情報排程的快速收斂排程方法用在低密度奇偶校驗編碼之解碼器。另外,我們設計了是用於此方法的硬體架構適用於IEEE 802.16e,也是大家所知的全球互通微波存取。從電腦模擬結果顯示,提出的方法跟水平階層解碼演算法比約減少解碼次數46.92%在信號雜訊比為1分貝之下和最大解碼次數設為20。另外,我們方法的位元錯誤率也只有可忽略的退步。我們實作提出演算法於賽靈思公司的元件可編程邏輯閘陣列版上驗證其正確性。實作結果得知額外的硬體開銷跟記憶體使用很小。因為較低的解碼次數,整個系統的吞吐量也提高許多。跟原本動態情報排程設計比較,我們提出的演算法之複雜度是低得多,而可以在硬體上很容易實作。 | zh_TW |
dc.description.abstract | In this thesis, we propose the fast convergence scheduling method based on the novel technique named Informed Dynamic Scheduling for low-density parity-check code decoder. In addition, we design the hardware architecture to fit with the proposed method applied to IEEE 802.16e standard which is known as WiMAX. From the computer simulation result, the proposed method decreases the decoding iteration up to 46.92% compared with the horizontal layer decoding algorithm when Signal-to-noise ratio is 1dB and the maximum decoding iteration is 20. Furthermore, the BER performance of our method has only small degradation which can be ignored. We also implement the proposed algorithm on Xilinx FPGA board to verify the correctness. The implementation result shows that the extra hardware cost and memory usage is small. The total system throughput also improves because of the lower decoding iterations. Compare with the origin Informed Dynamic Scheduling method, the complexity of our proposed algorithm is much lower that can be implemented on the hardware easily. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T01:15:00Z (GMT). No. of bitstreams: 1 ntu-98-R96922096-1.pdf: 2484383 bytes, checksum: d979c53964a4d836a77f150de718d5a7 (MD5) Previous issue date: 2009 | en |
dc.description.tableofcontents | 中文摘要 i
ABSTRACT ii CONTENTS iii LIST OF FIGURES vi LIST OF TABLES viii Chapter 1 Introduction 1 1.1 Digital Communication System Overview 1 1.2 Low-Density Parity-Check (LDPC) Code 2 1.2.1 Introduction to LDPC Code 2 1.2.2 Representation of LDPC Code 3 1.2.3 Quasi-Cyclic LDPC Code (QC-LDPC) 6 1.3 Motivation of the Thesis 7 1.4 Thesis Organization 8 Chapter 2 LDPC Decode Algorithm and Schedule 9 2.1 Overview of LDPC Decode 9 2.2 Decode Algorithm 12 2.2.1 Sum-Product Algorithm 12 2.2.2 Min-Sum Algorithm 14 2.3 Decode Schedule 14 2.3.1 Two Phase Schedule 15 2.3.2 Horizontal Layer Schedule 16 2.4 LDPC Code Decode Performance 19 2.4.1 LDPC Code for IEEE 802.16e Standard 19 2.4.2 Software Simulation Result 21 2.4.3 Fixed Point Simulation Result 24 Chapter 3 Proposed Fast Convergence LDPC Decode Algorithm 27 3.1 Informed Dynamic Schedule (IDS) 27 3.1.1 Node-wise Residual Belief Propagation 27 3.1.2 Performance and Complexity Analysis 30 3.2 Low Complexity and Fast Convergence LDPC Decode Algorithm Based on IDS 32 3.2.1 Overview of Proposed Algorithm 32 3.2.2 Conditional Layer Propagation Algorithm 33 3.2.3 The Method to Update Row Decision Vector 36 3.3 Comparison between IDS and CLPA 39 Chapter 4 Hardware Architecture Design 41 4.1 Overview of Proposed Hardware Architecture 41 4.2 Memory Block 42 4.3 Row Operation Unit 44 4.4 Decision Update Unit 45 4.5 I/O Controller 46 4.6 Control Unit 47 4.7 System Schedule Scheme 49 Chapter 5 Software Simulation and Hardware Implementation 51 5.1 Software Simulation Results 51 5.1.1 Decode Iteration 52 5.1.2 BER Performance 54 5.2 FPGA Evaluation Platform 55 5.3 FPGA Design Flow 56 5.4 FPGA Implementation Result 59 Chapter 6 Conclusion and Future Work 61 6.1 Conclusion 61 6.2 Future Work 62 REFERENCE 63 | |
dc.language.iso | en | |
dc.title | 基於IEEE802.16e標準之快速收斂低密度奇偶校驗編碼硬體解碼器設計與實作 | zh_TW |
dc.title | Design and Implementation of a Fast Convergence LDPC Decoder for IEEE802.16e Standard | en |
dc.type | Thesis | |
dc.date.schoolyear | 97-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林宗男,廖俊睿,洪士灝 | |
dc.subject.keyword | 低密度奇偶校驗編碼,快速收斂,解碼器,全球互通微波存取,動態情報排程,錯誤更正碼, | zh_TW |
dc.subject.keyword | LDPC,Fast Convergence,Decoder,WiMAX,Informed Dynamic Scheduling,Channel Coding, | en |
dc.relation.page | 66 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2009-07-28 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
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