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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
| dc.contributor.author | Chung-Hsing Yang | en |
| dc.contributor.author | 楊承勳 | zh_TW |
| dc.date.accessioned | 2021-06-15T01:14:29Z | - |
| dc.date.available | 2012-07-29 | |
| dc.date.copyright | 2009-07-29 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-07-29 | |
| dc.identifier.citation | Bibliography
[1] M.-S. Chae, W. Liu, and M. Sivaprakasam, “Design Optimization for Integrated Neural Recording Systems,” IEEE J. Solid-state Circuits, vol. 43, no. 9, pp. 1931-1939, Sep., 2008. [2] P. Allen and D. Holberg, “CMOS Analog Circuit Design,” 2nd Edition, 2002, Oxford University Press, ISBN 0-19-511644-5. [3] M. Burns and G.-W. Roberts, “An Introduction to Mixed-Signal IC Test and Measurement,” 2001, Oxford University Press, ISBN 0-19-514016-8. [4] J.-B. Begueret, M. R. Benbrahim, Z. Li, F. Rodes, J.-P. Dom, “Converters Dedicated to Long-Term Monitoring of Strain Gauge Transducers,” IEEE J. Solid-state Circuits, vol. 32, no. 3, pp. 349-356, Mar., 1997. [5] V. Ferrari, D. Marioli, A. Taroni, “Oscillator-Based Interface for Measurand-Plus-Temperature Readout from Resistive Bridge Sensors,” IEEE Trans. on Instrumentation and Measurement, vol. 49, no. 3, pp. 585-590, 2002. [6] G.-K. Dehng, J.-M. Hsu, C.-Y. Yang, and S.-I. Liu, “Clock-deskew buffer using a SAR-controlled delay-locked loop,” IEEE J. Solid-state Circuits, vol. 35, no. 8, pp. 1128-1136, Aug., 2000. [7] T.-H. Lin, C.-K. Wu, and M.-C. Tsai, “A 0.8-V 0.25mW Current-Mirror OTA with 160-MHz GBW in 0.18-um CMOS,” IEEE Transactions on Transactions and Systems II: Express Briefs, vol. 54, pp.131-135, Feb, 2007. [8] S.-J. Bae, H.-J. Chi, Y.-S. Sohn, and H.-J. Park, “A VCDL-Based 60-760-MHz Dual-Loop DLL with Infinite Phase-Shift Capability and Adaptive-Bandwidth Scheme,” IEEE J. Solid-state Circuits, vol. 40, no. 5, pp. 1119-1129, Mar., 2005. [9] S. M. Taleie, T. Copani, B. Bakkaloglu, and S. Kiaei, “A bandpass Delta-Sigma RF-DAC with embedded FIR reconstruction filter,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 578–579, 2006. [10] Linear Technology LT3020. Linear Technology Corp. [Online]. Available: http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1003,C1040,C1055,P2492,D2083 [11] P. J. Lim, and B. A. Wooley, “A High-speed Sample-and-Hold Technique Using a Miller Hold Capacitance,” IEEE J. Solid-state Circuits, vol. 26, no. 4, pp. 643-651, April, 1991. [12] T.-S. Lee and C.-C. Lu, “A 1.5-V 50-MHz pseudo-differential CMOS sample-and-hold circuit with low hold pedestal,” IEEE Trans. on Circuit and System I, vol. 52, pp. 1752-1757, Sep., 2005. [13] A. D. Grasso, G. Palumbo and S. Pennisi, “Advances in Reversed Nested Miller Compensation,” IEEE Trans. on Circuit and System I, vol. 54, Jul 2007. [14] S. Jiang, M. A. Do, K. S. Yeo, and W. M. Lim, “An 8-bit 200-MSample/s Pipelined ADC with Mixed-Mode Front-End S/H Circuit,” IEEE Trans. on Circuit and System I, vol. 55, pp. 1420-1440, Jul., 2008. [15] C. J. B. Fayomi, G. W. ROBERTS and M. SAWAN, “A 1-V, 10-bit Rail-to-Rail Successive Approximation Analog-to-Digital Converter in Standard 0.18 um CMOS Technology,” IEEE Trans. on Circuit and System I, vol.1, pp.460-463, May 2001. [16] H.-J. Hsu, C.-C. Tu, and S.-Y. Huang, “A High-Resolution All-Digital Phase-Locked Loop with Its Application to Built-In Speed Grading for Memory,” Proc. of Int'l Symp. on VLSI Design, Automation, and Testing, pp. 267-270, Apr 2008. [17] M. D. Scott, B. E. Boser, and K. S. J. Pister, “An Ultralow-Energy ADC for Smart Dust,” IEEE J. Solid-state Circuits,Vol.38, No.7, pp.1123-1129, Jul. 2003. [18] P. Confalonieri, M. Zamprogno, F. Girardi, G. Nicollini, and A. Nagari, “A 2.7mW 1MSps 10b Analog-to-Digital Converter with Built-in Reference Buffer and lLSB Accuracy Programmable Input Ranges,” Proc. of European Solid-State Circuits Conf., pp. 255-258, Sep. 2004. [19] K. Abdelhalim, L. MacEachern, and S. Mahmoud, “A Nanowatt Successive Approximation ADC with Offset Correction for Implantable Sensor Applications,” IEEE Symp. on Circuits and Systems, pp. 2351-2354, May, 2007. [20] T. K., H. Roy, and T. H. Teo, “A 0.9V l00nW Rail-to-Rail SAR ADC for Biomedical Applications,” IEEE Symp. on Integrated Circuits, pp. 481-484, Sep., 2007. [21] B. Bechen, D. Weiler, T. v. d. Boom, and B. J. Hosticka, “A 10 bit very low-power CMOS SAR-ADC for capacitive micro-mechanical pressure measurement in implants,” Advances in Radio Science, pp.243-246, Sep, 2006. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42478 | - |
| dc.description.abstract | 本論文提出兩個內建自我校正功能之以時間為基礎的類比數位轉換器。藉由利用雙路徑延遲電路架構來校正非理想效應。提出一個線性的電壓時序轉換器以增加此TD-ADC的線性度。
這兩個晶片是以台積電點一八微米金氧半製程製作。第一個晶片消耗1.6毫安培，操作在1伏特供應電壓之下。取樣頻率是33千赫茲，可輸入之共模範圍從170毫伏特至310毫伏特。電路沒有missing code，電路面積是1.2 mm X 1.2 mm。第二個晶片消耗746.3微安培，操作在1伏特供應電壓之下。取樣頻率是400千赫茲，可輸入之共模範圍從200毫伏特至800毫伏特。當給定200千赫茲輸入頻率時，電路訊雜比是41 dB。面積是1.35 mm2。 | zh_TW |
| dc.description.abstract | This thesis presents two time-domain-based analog-to-digital converters (TD-ADCs) with build-in calibration function. The proposed TD-ADCs utilize dual delay architecture to calibrate the non-idealities. A linear voltage-to-delay circuit is proposed to enhance the linearity of the TD-ADC.
Both chips are fabricated in TSMC 0.18 um CMOS process. The first chip consumes 1.6 mA from 1-V supply. The sampling rate is 33 kHz and input common range is from 170 mV to 310 mV. There is no missing code and the area is 1.2 mm by 1.2 mm. The second one consumes 746.3 uA from 1-V supply. The sampling rate is 400 kHz and input common mode range is from 200 mV to 800 mV. With 200 kHz input frequency, the SNR is 41 dB. The area is 1.35 mm by 1.35 mm. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T01:14:29Z (GMT). No. of bitstreams: 1 ntu-98-R95943007-1.pdf: 5970743 bytes, checksum: 9e381c728568902d1958f655bba4b29b (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | Contents
致謝 i 中文摘要 iii Abstract iv Contents v List of Figures viii List of Tables xii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Fundamentals of Analog-to-Digital Converters (ADCs) 3 2.1 Introduction of Analog-to-Digital Converters 3 2.1.1 Resolution 4 2.1.2 Gain Error 4 2.1.3 Offset Error 5 2.1.4 Differential Nonlinearity (DNL) 5 2.1.5 Integral Nonlinearity (INL) 6 2.1.6 Quantization Error 6 2.1.7 Signal-to-Noise Ratio (SNR) 7 2.1.8 Signal-to-Noise and Distortion Ratio (SNDR or SINAD) 8 2.1.9 Effective Number of Bits (ENOB) 8 2.2 Review of Successive-Approximation Register (SAR) ADC 8 Chapter 3 A 6-bit Time-Domain-Based Analog-to-Digital Converter 10 3.1 The Proposed Time-Domain-Based Analog-to-Digital Converter 10 3.1.1 The Transition of TD-ADC 10 3.1.2 TD-ADC Operation Concept 11 3.1.3 The Architecture of the Proposed TD-ADC 11 3.1.4 TD-ADC Operation Procedure 14 3.2 Discussion on the non-idealities effects 15 3.2.1 Input voltage changes from V1 to V2 in constant temperature T1 15 3.2.2 Input voltage changes from V1 to V2 in constant temperature T2 18 3.2.3 Input voltage V1 in T1 and it changes into input voltage V2 in T2 21 3.3 Building block Designs 23 3.3.1 Pre-Amplifier 24 3.3.2 The Proposed Linear Voltage-to-Delay Circuits 27 3.3.3 Digital-to-Analog Converter (DAC) 30 3.3.4 Phase Detector (PD) 30 3.3.5 Successive Approximation Register (SAR) Counter [6] 32 3.4 Simulation Results 34 3.4.1 Simulation of the self-calibration of the TD-ADC 34 3.4.2 Pre-Amplifier Simulation 35 3.4.3 Delay Circuit Simulation 38 3.4.4 System Input/Output Relationship Simulation 40 3.5 Measurement Results 43 3.5.1 Testing Setup 43 3.5.2 Pad Configuration and Chip Micrograph 43 3.5.3 Power Supply Generator 45 3.5.4 Print Circuit Board Design (PCB) 46 3.5.5 Experimental Results of the 6-bit TD-ADC 46 Chapter 4 A 10-bit Time-Domain-Based Analog-to-Digital Converter 51 4.1 The Architecture of this 10-bit TD-ADC 51 4.1.1 Sample and Hold 52 4.1.2 The Proposed Linear Voltage-to-Delay Circuits 56 4.1.3 Digital-to-Analog Converter (DAC) 58 4.1.4 Phase Detector (PD) 59 4.1.5 Successive Approximation Register (SAR) Counter [6] 59 4.2 Simulation Results 60 4.2.1 Sample and Hold Simulation 60 4.2.2 Delay Circuit Simulation 62 4.3 Measurement Results 66 4.3.1 Testing Setup 66 4.3.2 Pad Configuration and Chip Micrograph 67 4.3.3 Print Circuit Board Design (PCB) 68 4.3.4 Experimental Results of the 10-bit TD-ADC 69 Chapter 5 Conclusions and Future Works 83 5.1 Conclusions 83 5.2 Future Works 83 5.2.1 The Architecture of the Proposed Open-Loop TD-ADC 83 5.2.2 TD-ADC Operation Procedure 84 5.2.3 Discussion on the non-idealities effects 85 Bibliography 86 | |
| dc.language.iso | zh-TW | |
| dc.subject | 類比數位轉換器 | zh_TW |
| dc.subject | 延遲 | zh_TW |
| dc.subject | 取樣保持電路 | zh_TW |
| dc.subject | 數位類比轉換器 | zh_TW |
| dc.subject | 連續漸進式 | zh_TW |
| dc.subject | 線性 | zh_TW |
| dc.subject | digital-to-analog converter | en |
| dc.subject | analog-to-digital converter | en |
| dc.subject | sample and hold | en |
| dc.subject | successive approximation | en |
| dc.subject | linear | en |
| dc.subject | delay | en |
| dc.subject | DAC | en |
| dc.title | 以CMOS 0.18微米製程實現1伏特以時間為基礎之類比數位轉換器與線性電壓時序轉換電路 | zh_TW |
| dc.title | 1 V Time-Domain-Based Self-Calibrated Analog-to-Digital Converter with Linear Voltage-to-Delay Circuits in 0.18-um CMOS Technology | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 曾英哲,陳信樹(Hsin-Shu Chen) | |
| dc.subject.keyword | 類比數位轉換器,延遲,取樣保持電路,數位類比轉換器,連續漸進式,線性, | zh_TW |
| dc.subject.keyword | analog-to-digital converter,delay,sample and hold,digital-to-analog converter,DAC,successive approximation,linear, | en |
| dc.relation.page | 88 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2009-07-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-98-1.pdf 未授權公開取用 | 5.83 MB | Adobe PDF |
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