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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 施吉昇(Chi-Sheng Shih) | |
dc.contributor.author | Chih-Hung Teng | en |
dc.contributor.author | 鄧智鴻 | zh_TW |
dc.date.accessioned | 2021-06-15T00:51:29Z | - |
dc.date.available | 2008-09-02 | |
dc.date.copyright | 2008-09-02 | |
dc.date.issued | 2008 | |
dc.date.submitted | 2008-08-12 | |
dc.identifier.citation | [1] R. J. M. Rim and R. D. Leone, “Optimal allocation and binding in high-level synthesis,”
in 29th ACM/IEEE Conference on Design Automation, pp. 120–123, 1992. [2] J. G. DAmbrosio and X. Hu, “Configuration-level hardware/software partitioning for real-time systems,” in Proc. Int. Workshop Hardware-Software Co-Design, pp. 34–41, 1994. [3] B. P. Dave, G. Lakshminarayana, and N. K. Jha, “COSYN: Hardware-software cosynthesis of embedded systems,” in Conference on Design Automation, pp. 703–708, IEEE, 1997. [4] R. J. Cloutier and D. E. Thomas, “The combination of scheduling, allocation, and mapping in a single algorithm,” in 27th ACM/IEEE conference on Design automation, pp. 71–76, 1991. [5] W. Wolf, “An architectural co-synthesis algorithm for distributed, embedded computing systems,” IEEE Transactions on VLSI Systems, vol. 5, pp. 218–229, June 1997. [6] T. Jian-Jia Chen, “Allocation cost minimization for periodic hard real-time tasks in energy-constrained dvs systems,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 05-09, 2006. [7] Y.-A. CHEN, “System-level synthesis algorithms for real-time soc design,” 2006. [8] P. H. Chou, R. B. Ortega, and G. Borriello, “The chinook hardware/software cosynthesis system,” in Eighth International Symposium on System Synthesis, IEEE, 1995. [9] R. Ernst, J. Henkel, and T. Benner, “Hardware-software cosynthesis for microcontrollers,” in The Morgan Kaufmann Systems On Silicon Series, pp. 18–29, IEEE, 2001. [10] R. K. Gupta and G. D. Micheu, “Hardware-software cosynthesis for digital systems,” in IEEE Design and Test of Computers, pp. 29–41, IEEE, 1993. [11] P. Prabhakaran and P. Banerjee, “Parallel algorithms for force directed scheduling of flattened and hierarchical signal flow graphs,” in International Conference on Computer Design, pp. 66–71, 1996. [12] Y. Xie and W. Wolf, “Asicosyn: Co-synthesis of conditional task graphs with custom asics,” in ASIC, 2001. Proceedings. 4th International Conference, pp. 130–135, 2001. [13] Y. Xie andW.Wolf, “Allocation and scheduling of conditional task graph in hardware/ software co-synthesis,” in Design, Automation and Test in Europe, pp. 620– 625, 2001. [14] D. A. Patterson and J. L. Hennessy, Computer Organization and Design : The hardware/ software interface 2nd edition. Morgan Kaufman Publishers, Inc. [15] M. S. Lam, “Software pipelining:an effective scheduleing techique for vliw machines,” 1988. [16] B. R. Rau, “iterative modulo shceduling: an algorithm for software pipelining loops,” in international symposium on Microachitecture Proceedings of the 27th annual international symposium on Microachitecture, pp. 63–74, 1994. [17] V. H. Allan, “Software pipelining,” in ACM press, pp. 367–432, 1995. [18] “Lingo 8.0,” http://www.lindo.com. [19] V. V. Vazirani, Approximation Algorithms. Springer, 2001. [20] G. B. Dantzig and M. N. Thapa, Linear Programming 1: Introduction. Springer Verlag, 1997. [21] P. T. Gary J. Sullivan and A. Luthra, “The h.264/avc advanced video coding standard: Overview and introduction to the fidelity range extensions,” in SPIE Conference on Applications of Digital Image Processing, 2004. [22] S. Y. Xiaoli Zhao, Pin Tao and F. Kong, “Computation offloading for h.264 video encoder on mobile devices,” in IMACS Multiconference on Computational Engineering in Systems Applications(CESA), 2006. [23] “Arm processor overview.” http://www.arm.com/products/CPUs/index.html. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42185 | - |
dc.description.abstract | 多媒體消費性電子產品非常普及,多數的嵌入式系統都有多媒體工作在其上運行。因此如何做出具有足夠的運算能力且低成本的多媒體嵌入式系統是非常重要的議題。由於不同運算單元擅長執行的項目不同,現在的趨勢是使用多種不同的運算單元來組成嵌入式系統。然而在異質多運算單元的考量下,設計多媒體嵌入式系統並且讓成本最佳化是非常困難的問題。過去的研究有發明一些方法來解決這個問題並且有不錯的表現,但它們並沒有考慮管線設計的可能性。本篇研究提出了一個演算法,它將管線設計列入考量,設計出低成本且有足夠運算能力的多媒體嵌入式系統設。管線設計的概念是使獨立的工作平行地的運作,這放寬了每一個工作的回應時間的限制,並且使得成本可以更進一步地降低。我們做了各種模擬實驗,結果數據都顯示出我們所提供的設計方法可以得出相當好的系統設計。同時顯示了,比起不考量管線設計,將管線設計列入考量確實在各方面都有更進一步的改善。 | zh_TW |
dc.description.abstract | Multimedia electronic products are very popular now, and most of the embedded systems run multimedia tasks. Designing multimedia embedded systems with sufficient processing power and low allocation cost in hardware/software co-design flow is important to designers. It is a trend to use multi-PE for a multimedia task, because different PEs are good at executing different functionalities. However, allocation cost minimization problem for multimedia tasks in heterogeneous multi-PE embedded systems is a NP-hard problem. Previous work achieve good performance in this problem under consideration of sequential execution. However, we propose a approach to solve this problem under consideration of pipelined schedule, which can be used to exploit the benefit of parallel execution to relax the constraint of the response time and further reduce the allocation cost. The experimental results show that our approach could derive solutions with allocation costs close to those of optimal solutions. Moreover, our approach achieves lower cost and can handle all legal input instances than those who only consider sequential execution, because the pipelined schedule is taken into consideration. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T00:51:29Z (GMT). No. of bitstreams: 1 ntu-97-R95922107-1.pdf: 1083880 bytes, checksum: 12222871d078c376d2c27488a4519dc0 (MD5) Previous issue date: 2008 | en |
dc.description.tableofcontents | List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix List of Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Objective and Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Chapter 2 Background and RelatedWork . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Related work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 3 Problem Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1.1 Processing Element Models . . . . . . . . . . . . . . . . . . . . . . 11 3.1.2 Task Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Problem Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 NP-hardness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Chapter 4 The Pipelining-oriented Algorithm . . . . . . . . . . . . . . . . . . . 17 4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 Problem analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 Pipeline Scheduling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 Allocation Cost Minimization algorithm . . . . . . . . . . . . . . . . . . . 23 4.5 Legality of Input Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Chapter 5 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 High Level System Design for H.264 Encoder . . . . . . . . . . . . . . . . 31 5.1.1 Experiment setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.2 Experiment result . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2 Optimality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2.1 Experiment setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2.2 Experiment result . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 Capability of Handling Legal Input Instances . . . . . . . . . . . . . . . . 35 5.3.1 Experiment setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.2 Experiment result . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.4 Comparison of The Allocation Cost . . . . . . . . . . . . . . . . . . . . . . 36 5.4.1 Experiment setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.4.2 Experiment result . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Chapter 6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2 FutureWork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 | |
dc.language.iso | en | |
dc.title | 多媒體嵌入式系統之並行排程與成本最佳化設計 | zh_TW |
dc.title | Allocation Cost Minimization and Pipelined Scheduling for Multimedia Embedded System Design | en |
dc.type | Thesis | |
dc.date.schoolyear | 96-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃悅民,郭大維,洪士灝 | |
dc.subject.keyword | 軟硬體分割,硬體成本最佳化,管線設計,多媒體,嵌入式系統, | zh_TW |
dc.subject.keyword | HW/SW partition,allocation cost minimization,pipelined schedule,multimedia task,embedded system, | en |
dc.relation.page | 44 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2008-08-12 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
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