請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42123
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 盧信嘉(Hsin-Chia Lu) | |
dc.contributor.author | Kuan-Cheng Tseng | en |
dc.contributor.author | 曾冠澄 | zh_TW |
dc.date.accessioned | 2021-06-15T00:48:00Z | - |
dc.date.available | 2008-09-02 | |
dc.date.copyright | 2008-09-02 | |
dc.date.issued | 2008 | |
dc.date.submitted | 2008-08-21 | |
dc.identifier.citation | [1] Lap Kun Yeung and Ke-Li Wu, “A Compact Second-Order LTCC Bandpass Filter With Two Finite Transmission Zeros,” IEEE Transactions on Microwave Theory and Techniques, vol. 51, issue 2, part 1, pp. 337–341, Feb. 2003.
[2] Reinhard Kulka, Matthias Rittweger, Peter Uhlig, and Carsten Günner, LTCC-Multilayer Ceramic for Wireless and Sensor Applications. IMST GmbH, http://www.ltcc.de, ltcc@imst.de, Dec. 2001. [3] Peter Hagn, Andreas Przadka, Volker Gebhardt, and Ulrich Bauernschmitt, “Ceramics: The Platform for Duplexers and Frontend-Modules,” Proceedings of 2002 IEEE Ultrasonics Symposium, Oct. 2002, vol. 1, pp. 1–10. [4] Wonjong Kim and Hyunchul Shin, “Hierarchical LVS Based On Hierarchy Rebuilding,” Proceedings of 1998 Asia and South Pacific Design Automation Conference (ASP-DAC '98), Feb. 1998, pp. 379–384. [5] Yongseok Choi, Ikjae Chun, and Bogwan Kim, “Rectangle-based Hierarchical Layout Extraction Algorithm,” Journal of the Korean Physical Society, vol. 41, no. 6, pp. 988–992, Dec. 2002. [6] Yung-Shuen Chang, The extraction of inductors and capacitors from layout of microwave multi-layer circuits. Master Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, July 2007. [7] http://en.wikipedia.org/wiki/Trapezoid [8] Marko Lamot and Hermes Softlab, “An Overview of Triangulation Algorithms for Simple Polygons,” Proceedings of 1999 IEEE International Conference on Information Visualization, July 1999, pp. 153–158. [9] Nancy M. Amato, Michael T. Goodrich, and Edgar A. Ramos, “Linear-Time Triangulation of a Simple Polygon Made Easier Via Randomization,” Proceedings of 2000 Annual ACM Symposium on Computational Geometry (SoCG '00), June 2000, pp. 201–212. [10] Chris Worman, “Decomposing Polygons Into Diameter Bounded Components,” Proceedings of 2003 Canadian Conference on Computational Geometry (CCCG '03), Aug. 2003, pp. 103–106. [11] San-Yuan Wu and Sartaj Sahni, “Fast Algorithms to Partition Simple Rectilinear Polygons,” VLSI Design, vol. 1, no. 3, pp. 193–215, 1994 [12] Joseph O'Rourke and Geetika Tewari, “Partitioning Orthogonal Polygons into Fat Rectangles in Polynomial Time,” Proceedings of 2002 Canadian Conference on Computational Geometry (CCCG '02), Aug. 2002, pp. 97–100. [13] H. Lipson and M. Shpitalni, “Decomposition of a 2D polygon into a minimal set of disjoint primitives,” Proceedings of 1996 Conference on Set-Theoretic Solid Modeling (CSG '96), Apr. 1996, pp. 65–82. [14] Jia-Ming Chang, The back-end of layout vs. schematic checker for microwave multi-layer circuits:schematic mapping. Master Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, Jan. 2008. [15] Antonin Guttman, “R-Trees:A Dynamic Index Structure for Spatial Searching,” Proceedings of 1984 ACM SIGMOD International Conference on Management of Data, June 1984, pp. 599–609. [16] Timos Sellis, Nick Roussopoulos, and Christos Faloutsos, “The R+-Tree:A Dynamic Index for Multi-Dimensional Objects,” Proceedings of 1987 International Conference on Very Large Data Bases, Sep. 1987, pp. 507–518. [17] Norbert Beckmann, Hans-Peter Kriegel, Ralf Schneider, and Bernhard Seeger, “The R*-tree:An Efficient and Robust Access Method for Points and Rectangles,” Proceedings of 1990 ACM SIGMOD International Conference on Management of Data, May 1990, pp. 322–331. [18] R. A. Finkel and J. L. Bentley, 'Quad Trees:A Data Structure for Retrieval on Composite Keys,' Acta Informatica, vol. 4, no. 1, pp 1–9, Apr. 1974. [19] http://en.wikipedia.org/wiki/Design_rule_checking [20] http://en.wikipedia.org/wiki/GDSII [21] http://en.wikipedia.org/wiki/Sweep_line_algorithm [22] Tzu-Wei Chao, Flip-chip transition measurement and design of performance improved inductors and higher process tolerance coupled mutual inductors in multilayer structure. Master Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, July 2006. [23] Albert Sutono, Joy Laskar, and W. R. Smith, “Design of Miniature Multilayer On-Package Integrated Image-Reject Filters,” IEEE Transactions on Microwave Theory and Techniques, vol. 51, issue 1, part 1, pp. 156–162, Jan. 2003. [24] Chien-Wei Huang, Differential bandpass filters for WLAN and antenna switch module for GPRS applications using LTCC process. Master Thesis, Graduate Institute of Electronics Engineering, National Taiwan University, July 2006. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42123 | - |
dc.description.abstract | 本篇論文可以分為兩大部分。第一部份是關於微波多層電路佈局圖中基本形狀的萃取與網路連結圖的生成。此部份應用計算幾何的策略去設計演算法來辨識電路佈局圖中的基本形狀,並將所有的基本形狀連接成一個完整的網路連結圖。第二部份為網路連結圖的後續應用。本論文中的主要應用為檢查各連接埠間直流電是否相通、電容結構的萃取、電容值的估計、電感結構的萃取、電感元件的資訊萃取與自動生成以佈局圖為基礎的電路圖。基本形狀包含矩形與簡單多邊形,可萃取的電路元件包含電容、導線、電感、連通柱、連接埠與接地面。此兩部份為佈局圖對電路圖檢查之前段作業。 | zh_TW |
dc.description.abstract | There are two parts in this thesis. The first part is about the fundamental shape extraction from layout of microwave multi-layer circuit and the generation of net-list diagram. This part applies methodologies of computational geometry to design algorithms to identify the fundamental shapes from layout of circuit, and then connect all fundamental shapes into a complete net-list diagram. The second part is the post-applications of the net-list diagram. The main applications in this thesis are direct current path connectivity check, capacitor structure identification, capacitance estimation, inductor structure identification, inductor segment information extraction, and automatic layout-based schematic generation. The fundamental shapes include rectangles and simple polygons and the extractable circuit components include capacitors, wires, inductors, vias, ports, and ground. These two parts formed the front-end of Layout Versus Schematic (LVS) checking. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T00:48:00Z (GMT). No. of bitstreams: 1 ntu-97-R95943070-1.pdf: 9564428 bytes, checksum: 7801afc4d10a69ad6add25a1614c326e (MD5) Previous issue date: 2008 | en |
dc.description.tableofcontents | Chapter 1 Introduction ............ 1
1.1 Background ............ 1 1.1.1 An Example of Microwave Multi-Layer Circuit ............ 1 1.1.2 Introduction of LTCC Technology ............ 3 1.1.3 Introduction of BCB Technology ............ 4 1.2 Purpose ............ 6 1.3 Related Work ............ 7 1.3.1 Layout Extraction ............ 7 1.3.2 Decomposition of Two-Dimensional Simple Polygon ............ 8 1.3.3 DC Path Connectivity Check ............ 11 1.4 Roadmap ............ 12 Chapter 2 Layout Extraction ............ 15 2.1 Basic Assumptions ............ 15 2.2 Extraction of Rectilinear Shapes ............ 16 2.3 Extraction of Irregular Shapes ............ 21 2.3.1 Extraction of Oblique Corner Wires ............ 21 2.3.2 Extraction of Real Irregular Forms ............ 24 2.4 Summarized Algorithm of Layout Extraction ............ 27 2.5 Uniqueness of Extracted Result ............ 30 2.6 Process of Net-List Generation ............ 30 2.6.1 Decision of Rectangular Connectivity ............ 30 2.6.2 Wire Identification ............ 35 2.6.3 Inclusion of Vias and Other Components ............ 37 2.7 Summarized Flow of Net-List Generation ............ 37 2.8 A Demonstration of Net-List Diagram ............ 38 Chapter 3 Post-Applications ............ 41 3.1 DC Path Connectivity Check ............ 41 3.2 Capacitor Related Issues ............ 42 3.2.1 Introduction of Capacitor Structures ............ 42 3.2.2 Identification of Capacitor Structures ............ 43 3.2.3 Removal of Redundant Capacitor Structures ............ 43 3.2.4 Capacitance Estimation ............ 45 3.3 Inductor Related Issues ............ 46 3.3.1 Introduction of Inductor Structures ............ 46 3.3.2 Identification of Inductor Structures ............ 48 3.3.3 Extraction of Inductor Segments ............ 57 3.4 Generation of Layout-Based Schematic ............ 60 Chapter 4 Overall Results ............ 65 4.1 LTCC Circuit Examples ............ 65 4.1.1 2.4 GHz Image-Reject Filter ............ 65 4.1.2 5.25 GHz Bandpass Filter ............ 71 4.1.3 Single Bandpass Filter ............ 76 4.2 BCB Circuit Examples ............ 78 4.2.1 2.4 GHz Lowpass Filter ............ 78 Chapter 5 Conclusion ............ 83 References ............ 85 | |
dc.language.iso | en | |
dc.title | 由微波多層電路佈局圖中萃取集總元件電路圖 | zh_TW |
dc.title | The Lump Elements Schematic Extraction from Layout of Microwave Multi-Layer Circuits | en |
dc.type | Thesis | |
dc.date.schoolyear | 96-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃俊郎(Jiun-Lang Huang),李建模(Chien-Mo Li) | |
dc.subject.keyword | 集總元件,佈局圖,電路圖,萃取,佈局圖對電路圖檢查,電容,電感, | zh_TW |
dc.subject.keyword | lump element,layout,schematic,extraction,LVS,capacitor,inductor, | en |
dc.relation.page | 87 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2008-08-22 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-97-1.pdf 目前未授權公開取用 | 9.34 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。