請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42079完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 劉志文 | |
| dc.contributor.author | Chih-Luen Hsu | en |
| dc.contributor.author | 許志綸 | zh_TW |
| dc.date.accessioned | 2021-06-15T00:45:31Z | - |
| dc.date.available | 2013-09-02 | |
| dc.date.copyright | 2008-09-02 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-08-27 | |
| dc.identifier.citation | [1] 何俊賢,“降壓型DC/DC轉換器之數位控制設計與分析”, 國立台灣大學電機工程學系研究所碩士學位論文, 2006.
[2] Robert W. Erickson, Dragan Maksimovic,“Fundamentals of Power Electronics”,second edition. [3] Mohan Undeland Robbins,“Power Electronics”, second edition . [4] 梁適安,“交換式電源供給器之理論與實務設計”,全華出版社, 2004. [5] 葉家安“數位式降壓型直流/直流轉換器之研製”, 國立台北科技大學電機工程系碩士班碩士學位論文, 2006. [6] Tsun-Hsiao Hsia, Hsien-Yi Tsai, Yu-Zheng Lin, Dan Chen and Wei-Hsu Chang,“Digital Compensation of a High-Frequency Voltage - Mode DC-DC Converter”, Power Electronics and Applications, 2007 European Conference . [7] Xilinx, INC. ,“Spartan-3A/3AN Starter Kit Board User Guide”. [8] Simone Buso, Paolo Mattavelli“Digital Control in Power Electronics” Morgan & Claypool Publishers. [9] Benjamin C. Kuo, “Automatic Control Systems”, seventh edition, John Wiley & Sons, INC. [10] Karl J. Åström,Björn Wittenmark,“AdaptiveControl”,second Edition. [11] 鄭信源, “Verilog硬體描述語言數位電路”, 儒林出版社, 2006. [12] 國家半導體公司, “FPGA技術介紹”. [13] Xilinx, INC. ,“ISE 10.1i Quick Start Tutorial”. [14] 鄭信源, “Verilog硬體描述語言數位電路”, 儒林出版社, 2006. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42079 | - |
| dc.description.abstract | 本論文欲探討直流/直流降壓型轉換器(DC/DC Buck Converter)的數位控制器設計，及設計過程中必須考量的問題。
文中以Xilinx公司生產的FPGA開發板(Spartan 3A)來實現數位控制器的三個主要部份－類比/數位轉換器(A/D Converter)、數位補償器(Digital Compensator)、數位脈波寬度調變(DPWM)。依受控體規格－輸入電壓12V，輸出電感560nH，輸出電容4800µF，觀察參考電壓為1V時的穩定負載、動態負載等輸出波形。 直流/直流降壓型轉換器之控制模式為電壓模式，本文將推導出其小訊號模型，根據受控體規格設計出適合的補償器，並根據增益規劃(Gain Scheduling)概念，建立一查表(Lookup Table)，視負載狀況調整補償器參數，達到簡單的可適性控制(Adaptive Control)。 | zh_TW |
| dc.description.abstract | The thesis focuses on the design of digital controller for DC/DC Buck converter，and discusses what should be taken into consideration during the design process.
In the thesis，the FPGA board (Spartan 3A) manufactured by Xilinx incorporation is used to implement the three parts of the digital controller－ A/D converter，digital compensator，digital pulse width modulator. With the specification for the control plan－ input voltage 12V，output inductance 560nH，output capacitance 4800uF,the output waveform for fixed load，dynamic load at 1V reference voltage is observed. The control mode of DC/DC Buck converter is using Voltage Mode. The small signal model is derived in the thesis and is used to make the proper design for the compensator, also, a lookup table is made from it according to the concept of Gain Scheduling. Parameters of the compensator is adjusted according to the load condition to achieve simple adaptive-control. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T00:45:31Z (GMT). No. of bitstreams: 1 ntu-97-J95921032-1.pdf: 2103479 bytes, checksum: 604fdb0e711b39c5c63686571845b38d (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | 摘要 .............................................i
Abstract ........................................ii 目錄 ...........................................iii 圖目錄 ...........................................v 表目錄 .........................................vii 第一章 緒論 ....................................1 1.1 研究動機與目的 ..........................1 1.2 論文架構 ................................3 第二章 直流/直流降壓型轉換器基本原..............4 2.1 簡介.........................................4 2.2 多項式轉換器 ...............................5 2.3 小訊號模型 .................................5 第三章 數位控制器設計 .......................10 3.1 控制器架構 .............................10 3.2 控制系統模型............................11 3.2.1 數位脈波寬度調變(DPWM) ............12 3.2.2 類比數位轉換器(ADC) ...............12 3.2.3 數位補償器(Digital Compensator) ...13 3.2.4 系統延遲 ..........................14 3.3 數位補償器設計 ..........................15 3.4 增益規劃(Gain Scheduling) ...............20 3.5 電腦模擬 ................................22 第四章 實驗結果 ...............................28 4.1 FPGA實驗平台簡介.........................28 4.2 FPGA實驗平台設計.........................34 4.3 實驗結果.................................38 第五章 結論與未來方向 .........................42 5.1 結論 ...................................42 5.2 未來研究方向 ...........................42 參考文獻 .......................................43 | |
| dc.language.iso | zh-TW | |
| dc.title | 以FPGA實現直流/直流降壓型轉換器之數位可適性控制 | zh_TW |
| dc.title | Digital and Adaptive Control for DC/DC Buck Converters
Based on FPGA | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉添華,邱煌仁 | |
| dc.subject.keyword | 降壓型轉換器,類比/數位轉換器,數位補償器,數位脈波寬度調變,增益規劃,查表,可適性控制, | zh_TW |
| dc.subject.keyword | Buck converter,A/D converter,digital compensator,digital pulse width modulation,Gain Scheduling,lookup table,adaptive control, | en |
| dc.relation.page | 43 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-08-27 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
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| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-97-1.pdf 目前未授權公開取用 | 2.05 MB | Adobe PDF |
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