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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 楊佳玲(Chia-Lin Yang) | |
dc.contributor.author | Yen-Ming Chen | en |
dc.contributor.author | 陳彥名 | zh_TW |
dc.date.accessioned | 2021-06-15T00:45:16Z | - |
dc.date.available | 2008-09-02 | |
dc.date.copyright | 2008-09-02 | |
dc.date.issued | 2008 | |
dc.date.submitted | 2008-08-26 | |
dc.identifier.citation | [1] http://www.xbitlabs.com/.
[2] T. Akenine-Moller and J. Strom. Graphics for the masses: A hardware rasterization architecture for mobile phones. In ACM Transactions on Graphics, 22(3), pages 801-808, 2003. [3] I. Antochi, B. Juurlink, and S. Vassiliadis. Selecting the optimal tile size for low-power tile-based rendering. In Proc. ProRISC, pages 1-6, 2002. [4] D. Blythe. The direct3d 10 system. ACM Trans. Graph., 25(3):724-734,2006. [5] K. Claypool and M. Claypool. On frame rate and player performance in first person shooter games. Springer Multimedia Systems Journal (MMSJ), Volume 13, Number 1, 2007. [6] V. M. del Barrio, C. Gonzalez, J. Roca, and A. Fernandez. Attila: a cycle-level execution-driven simulator for modern gpu architectures. In Proc. IEEE International Symposium on Performance Analysis of System and Software (ISPASS), pages 231-241, March 2006. 33 [7] Y. Gu and S. Chakraborty. A hybrid dvs scheme for interactive 3d games. In RTAS ’08: Proceedings of IEEE Real-Time and Embedded Technology and Applications Symposium. [8] Y. Gu and S. Chakraborty. Control theory-based dvs for interactive 3d games. In DAC ’08: Proceedings of the 45th annual conference on Design automation, pages 740-745, New York, NY, USA, 2008. ACM. [9] Y. Gu, S. Chakraborty, and W. T. Ooi. Games are up for dvfs. In DAC'06: Proceedings of the 43rd annual conference on Design automation, pages 598-603, New York, NY, USA, 2006. ACM. [10] Z. Hu, A. Buyuktosunoglu, V. Srinivasan, V. Zyuban, H. Jacobson, and P. Bose. Microarchitectural techniques for power gating of execution units. In ISLPED ’04: Proceedings of the 2004 international symposium on Low power electronics and design, pages 32-37, New York, NY, USA, 2004. ACM. [11] G. Humphrey, M. Houston, R. Ng, S. Ahern, R. Frank, P. Kirchner, and J. T. Klosowski. Chromium: A stream processing framework for interactive graphics on clusters of workstations. In ACM Transactions on Graphics, 21(3), pages 693-702, 2002. [12] E. Lindholm and S. Oberman. Nradeon r600, a 2nd generation unified shader architecture. In Hot Chips 19 Symp, August 2007. [13] M. Mantor. Nvidia geforce 8800 gpu. In Hot Chips 19 Symp, August 2007. [14] B. Mochocki, K. Lahiri, and S. Cadambi. Power analysis of mobile 3d graphics. In DATE ’06: Proceedings of the conference on Design, automation and test in Europe, pages 502-507, 3001 Leuven, Belgium, Belgium, 2006. European Design and Automation Association. [15] B. C. Mochocki, K. Lahiri, S. Cadambi, and X. S. Hu. Signature-based workload estimation for mobile 3d graphics. In DAC ’06: Proceedings of the 43rd annual conference on Design automation, pages 592-597, New York, NY, USA, 2006. ACM. [16] B.-G. Nam, J. Lee, K. Kim, S. J. Lee, and H.-J. Yoo. A low-power handheld gpu using logarithmic arithmetic and triple dvfs power domains. In GH ’07: Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware, pages 73-80, Aire-la-Ville, Switzerland, Switzerland, 2007. Eurographics Association. [17] M. Powell, S.-H. YANG, B. Falsafi, K. Roy, and T. N. Vijaykumar. Gated-vdd: A circuit technique to reduce leakage in deep-submicron cache memories. In ISLPED ’00: Proceedings of the 2000 international symposium on Low power electronics and design, 2000), pages = 90-95. [18] J. Roca, V. Moya, C. Gonzalez, C. Solis, A. Fernandez, and R. Espasa. Workload characterization of 3d games. In Proc. IEEE International Symposium on Workload Characterization (IISWC), pages 17-26, 2006. [19] J. W. Sheaffer, D. Luebke, and K. Skadron. A flexible simulation framework for graphics architectures. In HWWS ’04: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware, pages 85-94, New York, NY, USA, 2004. ACM. [20] J.-H. Sohn, J.-H. Woo, M.-W. Lee, H.-J. Kim, R. Woo, and H.-J. Yoo. A 155-mw 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications. Solid-State Circuits, IEEE Journal of, 41(5):1081-1091, May 2006. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42074 | - |
dc.description.abstract | 隨著製程進步,如何減少漏電(leakage)的問題將會更加嚴苛。在以往圖形處理器(GPU)的設計方面,主要都著重在動態耗電(dynamic power)方面的問題,以動態調整電壓及頻率(DVFS)以及時脈閘控(clock-gating)為主要的策略。在這篇論文中,我們使用電源閘控(power-gating)來減少漏電,電源閘控是將正在閒置的處理單元(functional unit)整個關掉來節省漏電。因為遊戲中場景的變化加上畫面更新頻率(frame rate)的目標,在每個畫面(frame)所需要的著色處理器(shader)資源數也會不一樣,因此我們設計一個歷史基準(history-based)的預測器來預測每個畫面所需要的圖形處理器資源數,藉此有機會將多餘的圖形處理器關掉以節省漏電。
我們的實驗結果呈現出透過我們的電源閘控策略,最多可以節省到15.2%的漏電,而關閉些許圖形處理器所造成的效能下降非常有限。 | zh_TW |
dc.description.abstract | As the technology continues to shrink, reducing leakage is critical to achieve energy efficiency. Previous works on low power GPU (Graphics Processing Unit) focuses techniques for dynamic power reduction, such as DVFS(Dynamic Voltage/Frequency Scaling), and clock gating. In this paper, we explore the potential of adopting architecture-level power-gating technique to reduce leakage power of GPU. Power-gating is to turn off a functional unit during its idle period. Due to different scene complexity, the required shader resources to achieve target frame rate varies among frames. Therefore, we adopt a history-based approach to predict required shader resources in a frame, and turn off redundant shader processors.
The experimental results show that the proposed power-gating strategies achieve significant leakage reduction with negligible performance degradation. To achieve longer execution time and better energy utilization, power management is becoming more and more important issue to both batterypowered devices and tethered equipments. As CMOS technology evolving, leakage power will be the dominant source of power dissipation. In this paper, we explore possible redundant shader resources in modern GPU with unified shader architecture from exploiting power-gating perspective. We demonstrate observed redundant shader units from Frame-Level, which could be power-gated further to save leakage. In Frame-Level, we show that under unified shader architecture, there still exists redundant shader processors due to imbalance workload among frames. By deciding number of active shader processors dynamically using simple history-based prediction, we show that maximum of 15.2% shader leakage power could be saved while meeting performance requirement. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T00:45:16Z (GMT). No. of bitstreams: 1 ntu-97-R95922125-1.pdf: 1548206 bytes, checksum: 375a24298e83d05f08b11eed31c5c600 (MD5) Previous issue date: 2008 | en |
dc.description.tableofcontents | Abstract i
1 Introduction 1 1.1 Overview of this Thesis 3 1.2 Organization of this Thesis 4 2 Related Works 5 3 Analysis of Power-Gating Opportunity 11 3.1 Overview of GPU with Unified Shader Architecture 11 3.2 Variation of Shader Computation in Frame-Level 15 3.3 Workload Variation in Frame-Level 18 3.4 Potential Energy Saving 21 4 Applying Power-gating Techniques in Frame-Level 24 4.1 Frame-Level: Shader Shutdown Technique 24 4.2 Implementation of Shader Shutdown Technique 26 5 Experimental Setup and Results 27 5.1 Simulation Environment 27 5.2 Trace Files 28 5.3 Results 29 6 Conclusion 32 Bibliography 33 | |
dc.language.iso | en | |
dc.title | 在圖形處理器中通用著色器之電源閘控策略 | zh_TW |
dc.title | Power Gating Strategies for Unified Shader Unit in GPU | en |
dc.type | Thesis | |
dc.date.schoolyear | 96-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 洪士灝(Shih-Hao Hung),簡韶逸(Shao-Yi Chien) | |
dc.subject.keyword | 圖形處理器,電源閘控,漏電, | zh_TW |
dc.subject.keyword | GPU,Power-Gating,Leakage, | en |
dc.relation.page | 36 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2008-08-27 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
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