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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 呂良鴻 | |
dc.contributor.author | Jih-Hsin Wang | en |
dc.contributor.author | 王日新 | zh_TW |
dc.date.accessioned | 2021-06-15T00:43:18Z | - |
dc.date.available | 2013-09-02 | |
dc.date.copyright | 2008-09-02 | |
dc.date.issued | 2008 | |
dc.date.submitted | 2008-08-29 | |
dc.identifier.citation | [1] D. M. Binkley, M. Bucher, and D. Foty, “Design-oriented characterization of CMOS over the continuum of inversion level and channel length,” in IEEE Int. Electron., Circuits, Syst. Conf., Dec. 2000, pp. 161–164.
[2] A.-S. Porret et al., “A low-power low-voltage transceiver architecture suitable for wireless distributed sensors network,” in IEEE Int. Circuits Syst. Symp., May 2000, vol. 1, pp. 56–59. [3] Y. Tsividis, K. Suyama, and K. Vavelidis, “A simple ‘reconciliation’ MOSFET model valid in all regions,” Electron. Lett., vol. 31, no. 6, pp. 506–508, Mar. 1995. [4] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. New York: Oxford Univ. Press, 1999. [5] T.-K. Nguyen et al., “CMOS low-noise amplifier design optimization techniques,” IEEE Trans. Microw. Theory Tech., vol. 52, no. 5, pp. 1433–1442, May 2004. [6] J. Lu and F. Huang, “Comments on ‘CMOS low-noise amplifier design optimization techniques’,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 7, pp. 3155–3155, Jul. 2006. [7] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998. [8] B. Razavi, RF microelectronics. Upper Saddle River NJ: Prentice Hall, 1998. [9] F.-J. Huang and K. K. O, “A 0.5-μm CMOS T/R switch for 900-MHz wireless applications,” IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 486–492, Mar. 2001. [10] Z. Li and et al., “5.8-GHz CMOS T/R switches with high and low substrate resistance in a 0.18-μm CMOS process,” IEEE Microwave and Wireless Components Chapter, vol. 13, no. 1, pp. 1–3, Jan. 2003. [11] F.-J. Huang and K. K. O, “Single-pole double-throw CMOS switches for 900-MHz and 2.4-GHz applications on p-silicon substrates,” IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 35–41, Jan. 2004. [12] T. Ohnakado and et al., “21.5-dBm power-handling 5-GHz transmit/ receive CMOS switch realized by voltage division effect of stacked transistor configuration with depletion-layer-extended transistors (DETs),” IEEE Journal of Solid-State Circuits, vol. 39, no. 4, pp. 577–584, Apr. 2004. [13] N. Talwalkar, C. Yue, H. Guan and S. Wong, “Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications,” IEEE Journal of Solid-State Circuits, vol. 39, no. 6, pp. 863–870, Jun. 2004. [14] M.-C. Yeh and et al., “A miniature low-insertion-loss, high-power CMOS SPDT switch using floating-body technique for 2.4-and 5.8-GHz applications,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 451–454, Jun. 2005. [15] Z. Li and K. K. O, “15-GHz fully integrated nMOS switches in a 0.13-μm CMOS process,” IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 2323–2328, Nov. 2005. [16] M.-C. Yeh and et al., “Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance,” IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 1, pp. 31-39, Jan. 2006. [17] Y. Jin and C. Nguyen, “Ultra-compact high-linearity high-power fully integrated DC-20-GHz 0.18-μm CMOS T/R switch,” IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 1, pp. 30-36, Jan. 2007. [18] B.-W. Min and G. M. Rebeiz, “Ka-band low-loss and high-isolation 0.13- μm CMOS SPST/SPDT switches using high substrate resistance,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 569-572, June 2007. [19] T. Tokumitus, I. Toyoda and M. Aikawa, “A low-voltage, high-power T/R-switch MMIC using LC resonators,” IEEE Transactions on Microwave Theory and Techniques, vol. 43, no. 5, pp. 997-1003, May 1995. [20] H.-H. Hsieh and L.-H. Lu, “A high-performance CMOS voltage-controlled oscillator for ultra-low-voltage operations,” IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 3, pp. 467-473, Mar. 2007. [21] N. Stanic, P. Kinget and Y. Tsividis, “A 0.5 V 900 MHz CMOS receiver front end,” IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 228-229, June 2006. [22] H.-H. Hsieh and L.-H. Lu, “A high-performance CMOS voltage- controlled oscillator for ultra-low-voltage operations,” IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 3, pp. 467-473, March 2007. [23] H.-H. Hsieh and L.-H. Lu, “Design of ultra-low-voltage RF frontends with complementary current reused architectures,” IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 7, pp. 1445-1458, July 2007. [24] T. K. K. Tsang and M. N. El-Gamal, “Gain and frequency controllable sub-1 V 5.8 GHz CMOS LNA,” IEEE International Symposium on Circuits and Systems, vol. 4, pp. IV-795-IV798, May 2002. [25] D. Linten and et al., “Low-power 5 GHz LNA and VCO in 90 nm RF CMOS,” IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 372-375, June 2004. [26] T. Taris and et al., “A 1-V 2GHz VLSI CMOS low noise amplifier,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 123-126, Jun. 2003. [27] K. Ohsato and T. Yoshimasu, “Internally matched, ultralow dc power consumption CMOS amplifier for L-band personal communications,” IEEE Microwave and Wireless Components Chapters, vol. 14, no. 5, pp. 204-206, May 2004. [28] D. Wu and et al., “A 0.4-V low noise amplifier using forward body bias technology for 5 GHz application,” IEEE Microwave and Wireless Components Chapters, vol. 17, no. 7, pp. 543-545, July 2007. [29] B. Razavi, Design of analog CMOS integrated circuits. New York: McGraw-Hill, 2001. [30] G. Gonzalez, Microwave transistor amplifiers: analysis and design, 2nd ed. Upper Saddle River: Prentice-Hall, Inc., 1997. [31] B. Razavi, RF Microelectronics. Upper Saddle River NJ: Prentice Hall, 1998. [32] T.-K. Nguyen and et al., “CMOS low-noise amplifier design optimization techniques,” IEEE Transactions on Microwave Theory and Techniques, vol. 52, no. 5, pp. 1433-1442, May 2004. [33] J. Lu and F. Huang, “Comments on ‘CMOS low-noise amplifier design optimization techniques’,” IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 7, pp. 3155, July 2006. [34] X. Li, S. Shekhar and D. J. Allstot, “Gm-boosted common-gate LNA and differential Colpitts VCO/QVCO in 0.18-mm CMOS,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2609-2619, Dec. 2005. [35] J. Crols and M. Steyaert, “A single-chip 900-MHz CMOS receiver front-end with a high-performance low-IF topology,” IEEE J. Solid-State Circuits, vol.30, no.12, pp. 1483-1492, Dec. 1995. [36] F. Tillman and H. Sjöland, “A polyphase filter based on CMOS inverters,” 23rd IEEE NORCHIP Conference, pp. 12-15, Nov. 2005. [37] D. I. Sanderson, R. M. Svitek, and S. Raman, “A 5-6-GHz polyphase filter with tunable I/Q phase balance,” IEEE Microwave and Wireless Components Letters, vol.14, no.7, pp. 364-366, Jul. 2004. [38] B. Razavi, Design of analog CMOS integrated circuits. New York: McGraw-Hill, 2001. [39] C. –Y. Chou, C. –Y. Wu, “Design of wide-band and low-power CMOS active polyphase filter,” IEEE Transactions On Circuits And Systems – I: Regular Papers, pp. 825-833, May. 2005. [40] F. Behbahani et al., “CMOS mixers and polyphase filters for large image rejection,” IEEE J. Solid-State Circuits, vol.36, no.6, pp. 873-887, Jun. 2001. [41] K. Komoriyama, E. Yoshida, E. Yashiki, and H. Tanimoto, “A very wideband fully balanced active RC polyphase filter based on CMOS inverters in 0.18-um CMOS technology,” IEEE Symposium on VLSI Circuits, pp. 98-99, Jun. 2007. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/42038 | - |
dc.description.abstract | 本篇論文介紹低電壓低功率射頻前端接收器之設計問題與實作。在此論文中,不同的電路技巧與架構被提出與實現以降低功率消耗並解決供應電壓不足的問題。本論文共分為六個章節,首先第一章大致介紹論文組織與架構,第二章則回顧與低電壓低功率射頻前端接收器有關的背景知識。
第三章提出一個適用於低電壓之射頻接收/發射切換開關。利用非對稱之電感-電容共振腔架構,除了解決在低供應電壓下電晶體開關特性不佳之問題,更可有效達成在接收端時的低輸入損耗,與發射端之高線性度。此電路以0.18-um標準互補式金氧半導體製程實現,同時量測結果也會於本章討論並呈現。 第四章則分析低電壓之低雜訊放大器之設計問題與架構。以折疊-串疊架構為主軸,本章提出在極低功率(約1毫瓦)下,最大化電路效能之可能。另外以折疊-串疊加上一增益加強迴路以達到高增益之架構亦在此章被討論。兩種低雜訊放大器之架構均以0.18-um標準互補式金氧半導體製程實作並且加以量測。 第五章包含一個低中頻多相位濾波器之設計與實作結果。此設計採用主動式電路以降低多級濾波器串聯時,後級對前級之負載效應所造成之訊號損耗。與被動式電阻-電容多相位濾波器比較,本章所提出之架構可大幅降低達到相同信號增益下之功率消耗。 最後,結論在第六章提出並總結。 | zh_TW |
dc.description.abstract | This thesis introduces the design issues and implementation of low-voltage low-power radio frequency receiver front-end circuits. To operate in heavily reduced supply voltage, different architectures and design techniques have been proposed. The thesis is organized by six chapters. The first chapter illustrates the current technology trend as an introduction. In chapter 2, the background knowledge for low-voltage low-power design is overviewed.
In chapter 3, a low-voltage radio frequency transmit/receive switch is proposed. Using inductor/capacitor resonators, this architecture successfully resolves the limitation of poor on/off characteristics of transistor due to low supply voltage. Furthermore, the switch exhibits a low insertion loss in the receive path, as well as a high power handling capability in transmit path. The circuit is implemented using a standard 0.18-um CMOS process. The experimental results are also included in this chapter. In chapter 4, design issues and architectures of low-noise amplifier (LNA) are discussed and analyzed. Based on folded cascode architecture, methods to maximizing LNA characteristics with very low power dissipation (~1mW) are proposed. In addition, a folded cascode LNA adding a gain-enhancement loop is also realized in this chapter. Both circuits are implemented with a standard 0.18-um CMOS process and the measurement results are presented in this chapter. In chapter 5, a low-intermediate frequency polyphase filter incorporating an active structure is implemented to decrease the signal loss due to the loading effect while cascading multistages. Compared with a traditional passive R-C polyphase filter, this low-voltage active polyphase filter using a 0.18-um CMOS process exhibits much lower power dissipation while achieving the same signal gain level. Finally, conclusions are discussed in Chapter 6. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T00:43:18Z (GMT). No. of bitstreams: 1 ntu-97-R95943090-1.pdf: 1900485 bytes, checksum: 87100977a367a054e5e86bed42d4649e (MD5) Previous issue date: 2008 | en |
dc.description.tableofcontents | Acknowledgement………………………………I
Abstract………………………………………III Table of Contents…………………………VII List of Figures……………………………IX List of Tables………………………………XIII CHAPTER 1 INTRODUCTION………………………………………………1 1.1 MOTIVATION………………………………………………1 1.2 THESIS OVERVIEW………………………………………2 CHAPTER 2 BACKGROUND……………………………………………3 2.1 BASIC CONCEPTS ……………………………………3 2.1.1 MOSFETS AT VARIOUS INVERSION LEVELS……………3 2.1.2 NOISE FIGURE………………………………………………6 2.1.3 LINEARITY…………………………………… 9 2.2 FORWARD BODY BIAS TECHNIQUE……………………10 2.3 RF RECEIVER ARCHITECTURES IN LOW-VOLTAGE LOW-POWER DESIGNS..13 CHAPTER 3 A 5.2-GHz CMOS T/R Switch for Ultra-Low-Voltage Operations..........................15 3.1 INTRODUCTION ………………………………………15 3.2 THE LC-RESONATOR AS A SWITCH…………………17 3.3 THE PROPOSED T/R SWITCH…………………………23 3.4 EXPERIMENTAL RESULTS…………………………31 3.5 CONCLUSION…………………………………………37 CHAPTER 4 GAIN-ENHANCEMENT TECHNIQUES FOR CMOS FOLDED CASCODE LNAS AT LOW-VOLTAGE OPERATIONS……………39 4.1 INTRODUCTION……………………………………40 4.2 THE CONVENTIONAL FOLDED CASCODE LNA……………………41 4.3 FOLDED CASCODE LNA WITH FORWARD BODY BIAS………42 4.4 THE LNA WITH GM-BOOSTING TECHNIQUE…………55 4.5 EXPERIMENTAL RESULTS……………………………62 CHAPTER 5 A 0.6-V Active Polyphase Filter For Low-IF Receivers…………69 5.1 INTRODUCTION……………………………………69 5.2 PASSIVE R-C NETWORK POLYPHASE FILTER………70 5.3 THE PROPOSED ACTIVE POLYPHASE FILTER………73 5.4 EXPERIMENTAL RESULTS……………………………77 5.5 CONCLUSION…………………………………………79 CHAPTER 6 CONCLUSION..........................81 BIBLIOGRAPHY ………………………………………………………83 | |
dc.language.iso | en | |
dc.title | 低電壓低功率之CMOS射頻接收器前端電路 | zh_TW |
dc.title | Low-Voltage Low-Power CMOS Radio Frequency Receiver Front-end Circuits | en |
dc.type | Thesis | |
dc.date.schoolyear | 96-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 鄭裕庭,郭建男,陳巍仁 | |
dc.subject.keyword | 低電壓,低功率,射頻,前端接收器, | zh_TW |
dc.subject.keyword | low voltage,low power,radio-frequency,receiver front-end, | en |
dc.relation.page | 86 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2008-08-29 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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