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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/41606
標題: | 實現於無線積體電路測試平台上之管線式類比數位轉換器數位校正技術與自我測試電路 Implementation of a Built-in-Self-Calibration Technique for 1-bit/stage Pipelined ADC in the Wireless IC Testing Platform |
作者: | Kuo-Yu Chou 周國裕 |
指導教授: | 黃俊郎 |
關鍵字: | 管線式類比數位轉換器,積體電路無線測試平台,積分非線性,微分非線性, pipelined ADC,DNL,INL,missing-decision-level,missing-transition-level,HOY, |
出版年 : | 2009 |
學位: | 碩士 |
摘要: | 在本論文中,我們實現了一個針對1-bit/stage的管線式類比數位轉換器的全數位校正技術的硬體電路至積體電路無線測試平台上(HOY)。它主要功能區塊有統計直方圖測試功能(Histogram Testing)、字碼失誤決策層功能(Missing-Dec- ision-Level)、字碼失誤轉變層功能(Missing-Transition-Level)、萃取失誤字碼功能(Extract the Number of Missing Codes) 、邊界字碼修正功能(Boundary Code Modification)、重疊字碼消除功能(Overlap Cancelation)、產生錯誤係數功能(Generate the Error Coefficients)、校正電路(Calibration Scheme)、積分非線性(INL)與微分非線性(DNL)計算電路。所實現的電路有別於傳統設計,有以下的特性,第一個是掃瞄原始輸入資料即時產生所有字碼對應(Code Hits)平均統計直方圖以獲取1 LSB值,第二個是二段式校正演算法,第三個是即刻同時(On
-the- Fly)與第一相位的數值進行積分非線性INL與DNL計算。基於上述特性,我們所實現的電路有以下重要貢獻:最佳的線性校正與匹配容忍、降低測試時間與硬體佔用(Hardware Overhead)、提高雜訊容忍、斜坡電路(Ramp)斜率無需限制。將電路燒入至積體電路無線測試平台上的FPGA,成為系統中DUT的輸入端。經由Wrapper界面電路與DEU溝通將測試結果,最大INL/DNL值,透過HOY無線傳輸將值送到ATE,最後由終端機上的測試程式讀取,在螢幕上正確地顯示測結果試數據。 In this thesis, an implemented fully digital calibration scheme verified in the wireless IC Testing Platform ─ HOY for the 1-bit/stage pipelined ADC is presented. The calibration design includes the Linear Histogram Testing, Missing-Decision-Level, Extracting the Number of Missing Codes, Boundary Code Modification, Overlap Cancelation, Generating the Error Coefficients, Compensation Code Output, INL/DNL Calculation. There are several novel phases in the implemented schemes, that is, the first phase is there are two levels, missing-decision-level and missing-transition-level, calibration algorithm, the second phase is collecting the total code hits to drive 1 LSB, and the third phase is on-the-fly INL/DNL calculation. The features with the above mentioned functional implementation can acquire best calibration linearity and best mismatch tolerance, degrade test time and hardware overhead, enhance noise tolerance and free strict slope constraints from the input ramp test signal circuit. The designs verified in the FPGA hardware of the DUT in the HOY platform transfer the test data to DEU by the wrapper circuit, and then pass data to ATE by the wireless RF circuit. The test program developed by Python program language in the Linux OS in the terminal can fetch the test result data, maximum INL/DNL, correctly to be shown in the screen. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/41606 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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