45度虛擬線路填充降低化學機械研磨平坦化金屬耦合電容

Abstract

虛擬金屬填充技術主要應用於晶片設計的後繞線階段，在現今晶圓製程相當著名，主要用來確保晶片內金屬線路密度的一致性並且降低晶片在化學機械研磨平坦化過程中所產生的厚度差異性。我們也必須確保虛擬金屬填充過程中的梯度密度，確保密度在一個特定大小的區域中的厚度差異性不能超過一定的值。這個值通常都由晶片製造廠建議。虛擬金屬填充將導致耦合電容的增加，過高的耦合電容將造成時間延遲近而影響整個晶片的效能。在本論文中，我們提出一套虛擬金屬填充設計流程與45度角虛擬金屬填充的貪婪演算法和強度導向演算法，此設計流程包括設計準備階段、虛擬區域抽取階段、以及虛擬線路填充階段。實驗結果顯示，強度導向演算法的45度電容模型擺放，將有效減少1.9%~14.1%的耦合電容。同時我們也用90度和180度虛擬金屬填充，結果顯示影響晶片效能13 到344兆分之一秒。實驗證實我們所提供的方法，有效減少耦合電容並維持晶片運作效能。

Dummy metal insertion is one of the latest methods to be commonly used in the post-layout step during design implementation. It is used to keep the metal den- sity within the chip area at a constant value and reduce the variation in thickness of chemical-mechanical planarization (CMP) [5]. During metal fill insertion, the gradient of metal density should be also considered to ensure that the density vari- ation is not above a threshold within a sliding window. This threshold is typically recommended by foundry [29]. However, the coupling capacitance is significantly increased by dummy metal insertion, and the increased coupling capacitance may cause timing failure in the chip's performance. This thesis proposes one metal fill insertion design flow and two algorithms, greedy and force-directed, for inserting the 45-degree metal fills (diagonal fills). The design flow includes three stages: the design preparation stage, the dummy fill region extraction stage and the dummy fill insertion stage. The force-directed algorithm which is applied in the dummy fill in- sertion stage considers the coupling capacitance as a weight and avoids the impact of the timing slack. Diagonal metal fills are simulated and it is concluded that they have less capacitance than 0-degree metal fills (parallel fills) and 90-degree metal fills (per- pendicular fills). Compared with 0- and 90-degree metal fills, 45-degree metal fills could reduce capacitance by 1.9%{14.1%. TNS (total negative slack) and WNS (worst negative slack) [22] are also maintained with 45-degree metal fills, whereas 0- and 90-degree metal fills increase the timing delay from 13 pico-seconds in ex- perimental test case of design3 [9] to 344 pico-seconds in experimental test case of design6. Design3 is the design with clock cycle of 2000 pico-seconds, whereas design6 is the design with clock cycle of 14000 pico-seconds. Experimental results based on commercial tools demonstrate that our proposed force-directed methods can decrease the coupling capacitance and improve timing performance.