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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/41291完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張耀文 | |
| dc.contributor.author | Po-Hung Lin | en |
| dc.contributor.author | 林柏宏 | zh_TW |
| dc.date.accessioned | 2021-06-15T00:15:20Z | - |
| dc.date.available | 2009-06-23 | |
| dc.date.copyright | 2009-06-23 | |
| dc.date.issued | 2009 | |
| dc.date.submitted | 2009-06-18 | |
| dc.identifier.citation | [1] F. Balasa, “Modeling non-slicing floorplans with binary trees,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 13–16, San Jose, CA, November 2000.
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/41291 | - |
| dc.description.abstract | 在現今類比佈局設計中，為了達到好的佈局品質和電路效能，在類比元件擺置的過程中，考慮佈局設計階層是非常重要的。為了降低元件間的不匹配，和電路對溫度和製程變異的敏感度而產生有害的寄生效應，在每個佈局階層中考量元件間的匹配、對稱、和相鄰接近，更是不可或缺的。此外，當整合功率和非功率元件在同一顆晶片時，如何使類比擺置達到理想的晶片溫度分佈，使得元件之間的溫度都能匹配，亦是一項重要的課題。
在本論文中，我們描述了一個考慮佈局設計階層的階層式類比電路之元件擺置方法，並提出全新的階層式二元樹 (HB*-tree) 和自動對稱可實行二元樹 (ASF-B*-trees) 來加以實現。為了達到元件間的匹配、(階層式)對稱、和(階層式)相鄰接近等最重要的類比擺置限制條件，以及理想的晶片溫度分佈，我們進一步提出：(1)一個以樣式為基礎的匹配擺制和繞線方法，以加速匹配元件群組，如電流鏡，之佈局圖的生成，(2)目前文獻中第一個線性時間可完成的封裝演算法，處理類比元件擺置，同時依據「對稱島」的概念考慮考慮對稱元件群組，如差動電路元件，的擺置，(3)目前文獻中第一個根據階層式電路元件群組，處理類比元件擺置，並探討元件相鄰接近和階層式二元樹 (HB*-tree) 的特性與其間的關係，(4)目前文獻中第一個直接對晶片溫度分佈做最佳化的溫度驅動的類比元件擺置方法。 根據基準評價電路所做的實驗結果顯示，我們所提出的階層式類比元件擺置方法和過去文獻中所提的方法相比，在處理元件間的匹配、(階層式)對稱、和(階層式)相鄰接近等類比元件擺置限制條件最有效率，同時可以在最短的時間內，得到最佳的類比電路效能及精確性，且最不易受到溫度梯度帶來的影響。 | zh_TW |
| dc.description.abstract | In modern analog layout design, it is very important to consider layout design hierarchy for better layout quality and circuit performance especially when conducting analog device placement. To reduce unwanted parasitic effects arising from device mismatches and circuit sensitivities due to thermal gradients and process variation, it is also essential to consider device matching, device symmetry, and device proximity in each hierarchy. In addition, when integrating power and non-power devices on the same chip, the preferred thermal profile should be further considered for better thermal device matching.
In this dissertation, we present a hierarchical analog placement approach with the consideration of layout design hierarchy by introducing the novel hierarchical B*-tree (HB*-tree) and automatically symmetric-feasible B*-tree (ASF-B*-tree) floorplan representations. To further achieve the most important layout constraints including, device matching, (hierarchical) device symmetry, and (hierarchical) device proximity, as well as the preferred thermal profile, we propose: (1) a pattern-based matching placement and routing approach to facilitate the layout generation of matching device groups, such as current mirrors, (2) the first linear-time packing algorithm for analog placement with symmetry constraints by introducing the symmetry-island formulation for symmetry device groups, such as differential circuits, (3) the first analog placement approach based on hierarchical circuit clustering by exploring the correlation between the proximity constraints and properties of HB*-trees, and (4) the first thermal-driven analog placement considering thermal device matching by directly optimizing the thermal profile on the chip. Experimental results based on the analog benchmark circuits show that our hierarchical analog placement approach is the most effective one to handle analog placement with matching, (hierarchical) symmetry, and (hierarchical) proximity constraints. It can achieve the best published runtime efficiency and analog circuit performance/accuracy with the least impact due to the thermal gradient. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T00:15:20Z (GMT). No. of bitstreams: 1 ntu-98-D94943034-1.pdf: 3264118 bytes, checksum: 6e6242c26814a7ed889557bdb73b7435 (MD5) Previous issue date: 2009 | en |
| dc.description.tableofcontents | Acknowledgements ii
Abstract (Chinese) iii Abstract v List of Tables x List of Figures xi Chapter 1. Introduction 1 1.1 Analog Layout Synthesis Flow . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Modern Analog Placement Requirements . . . . . . . . . . . . . . . . . . 2 1.2.1 Device Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2.2 Device Symmetry . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2.3 Device Proximity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.4 Hierarchical Device Constraints . . . . . . . . . . . . . . . . . . . . 5 1.2.5 Thermal Consideration . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 Analog Placement Techniques . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.1 Constructive Approach . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.2 Bounded Enumerative Approach . . . . . . . . . . . . . . . . . . . 8 1.3.3 Simulated-annealing Approach . . . . . . . . . . . . . . . . . . . . 8 1.4 Floorplan Representations in Analog Placement . . . . . . . . . . . . . . 8 1.4.1 Absolute Floorplan Representation . . . . . . . . . . . . . . . . . . 9 1.4.2 Topological Floorplan Representation . . . . . . . . . . . . . . . . 10 1.5 Overview of the Dissertation . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.5.1 Analog Placement with Pattern Routing for Matched Devices . . . 12 1.5.2 Analog Placement Based on Symmetry-Island Formulation . . . . . 12 1.5.3 Analog Placement based on Hierarchical Module Clustering . . . . 13 1.5.4 Thermal-driven Analog Placement Considering Device Matching . 13 1.6 Organization of the Dissertation . . . . . . . . . . . . . . . . . . . . . . . 14 Chapter 2. Analog Placement with Pattern Routing for Matched Devices 15 2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 Matching Device Extraction . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 Pattern-based Device Layout Generation . . . . . . . . . . . . . . . . . . 18 2.4.1 Pattern-based Matching Placement . . . . . . . . . . . . . . . . . . 18 2.4.2 Pattern-based Matching Routing . . . . . . . . . . . . . . . . . . . 18 2.5 Inter-device Placement and Routing . . . . . . . . . . . . . . . . . . . . . 22 2.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Chapter 3. Analog Placement Based on Symmetry-Island Formula- tion 26 3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.1 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.2 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2.1 Symmetry Constraints . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2.2 Symmetry Island . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 Placement of a Symmetry Group . . . . . . . . . . . . . . . . . . . . . . 34 3.4 The Hierarchical Framework . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.1 HB*-tree Representation . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.2 ASF-B*-tree Packing . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.4.3 HB*-tree Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.4.4 Consideration of Non-symmetry-island Placements . . . . . . . . . 47 3.5 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.1 HB*-tree Perturbation . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.2 ASF-B*-tree Perturbation . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.3 Contour Node Related Updates . . . . . . . . . . . . . . . . . . . . 53 3.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Chapter 4. Analog Placement based on Hierarchical Module Clus- tering 63 4.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.1.1 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.1.2 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.2 Hierarchical Module Clustering . . . . . . . . . . . . . . . . . . . . . . . 66 4.2.1 Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.2.2 Placement Requirements . . . . . . . . . . . . . . . . . . . . . . . 68 4.3 Placement Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.1 Hierarchical Framework . . . . . . . . . . . . . . . . . . . . . . . . 72 4.3.2 Hierarchical Packing . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.3.3 Hierarchical Perturbation . . . . . . . . . . . . . . . . . . . . . . . 75 4.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Chapter 5. Thermal-driven Analog Placement Considering Device Matching 82 5.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.1.1 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.1.2 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.2 Desired Thermal Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3 Thermal-driven Analog Placement . . . . . . . . . . . . . . . . . . . . . . 88 5.3.1 Thermal Profile Computation . . . . . . . . . . . . . . . . . . . . . 90 5.3.2 Thermal Profile Optimization . . . . . . . . . . . . . . . . . . . . . 92 5.3.3 Thermal-driven Matching Device Placement . . . . . . . . . . . . . 94 5.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Chapter 6. Concluding Remarks and Future Work 104 6.1 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Bibliography 107 Vita 114 Publication List 115 | |
| dc.language.iso | en | |
| dc.subject | 類比電路 | zh_TW |
| dc.subject | 擺置 | zh_TW |
| dc.subject | 平面規劃 | zh_TW |
| dc.subject | 實體設計 | zh_TW |
| dc.subject | Physical Design | en |
| dc.subject | Analog Circuit | en |
| dc.subject | Placement | en |
| dc.subject | Floorplanning | en |
| dc.title | 階層式類比電路之擺置 | zh_TW |
| dc.title | Hierarchical Analog Circuit Placement | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 97-2 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 郭斯彥,陳少傑,李鎮宜,徐爵民,王廷基 | |
| dc.subject.keyword | 實體設計,平面規劃,擺置,類比電路, | zh_TW |
| dc.subject.keyword | Physical Design,Floorplanning,Placement,Analog Circuit, | en |
| dc.relation.page | 115 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2009-06-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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