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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/40968
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor胡振國(Jenn-Gwo Hwu)
dc.contributor.authorChih-Hao Chenen
dc.contributor.author陳志豪zh_TW
dc.date.accessioned2021-06-14T17:09:21Z-
dc.date.available2009-07-30
dc.date.copyright2008-07-30
dc.date.issued2008
dc.date.submitted2008-07-29
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[18] W. Zhu, T. P. Ma, T. Tamagawa, Y. Di, J. Kim, R. Carruthers, M. Gibson and T. Furukawa, “HfO2 and HfAlO for CMOS : Thermal Stability and Current Transport, ” in IEDM Tech. Dig., pp. 20.4.1-20.4.4, 2001.
[19] M. S. Akbar, C. H. Choi, S. J. Rhee, S. A. Krishnan, C. Y. Kang, M. H. Zhang, T. Lee, I. J. Ok, F. Zhu, H. S. Kim, and J. C. Lee, “Electrical Performance and Reliability Improvement by Using Compositionally Varying Bi-Layer Structure of PVD HfSixOy Dielectric,” IEEE Electron Device Lett., vol. 26, pp. 166-168, Mar. 2005.
[20] P. F. Lee, J. Y. Dai, K. H. Wong, H. L. W. Chan, and C. L. Choy, “Study of interfacial reaction and its impact on electric properties of Hf–Al–O high-k gate dielectric thin films grown on Si,” Appl. Phys. Lett., vol. 82, pp. 2419-2421, Apr. 2003.
[21] C. S. Kuo, J. F. Hsu, S. W. Huang, L. S. Lee, M. J. Tsai, and J. G. Hwu, “High-k Al2O3 Gate Dielectrics Prepared by Oxidation of Aluminum Film in Nitric Acid Followed by High-Temperature Annealing,” IEEE Trans. Electron Devices, vol. 51, pp. 854-858, June 2004.
[22] J. Robertson, “Band offsets of wide-band-gap oxides and implications for future electronic devices,” J. Vac. Sci. Technol. B, vol. 18, pp. 1785-1791, May/Jun. 2000.
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[29] J. C. Chiang and J. G. Hwu, “Low temperature (<400 °C) Al2O3 ultrathin gate dielectrics prepared by shadow evaporation of aluminum followed by nitric acid oxidation,” Appl. Phys. Lett., vol. 90, pp. 102902-1-102902-3, Mar. 2007.
[30] C. H. Chang and J. G. Hwu, “Low Temperature Ultra-thin Hafnium Oxide Dielectrics by Sputtering of Hf Metal on Tilted Substrate Followed by Nitric Acid Oxidation then Anodization Compensation in D. I. Water,” in SSDM2007, F-5-4, pp. 780-781, Sept. 2007.
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[40] Y.P. Lin and J. G. Hwu, “Oxide-Thickness-Dependent Suboxide Width and Its Effect on Inversion Tunneling Current,” Journal of The Electrochemical Society, vol. 151, pp. G853-G857, Dec. 2004.
[41] H. Yang, H. Niimi, J. W. Keister, G. Lucovsky, and J. E. Rowe, “The Effects of Interfacial Sub-Oxide Transition Regions and Monolayer Level Nitridation on Tunneling Currents in Silicon Devices,” IEEE Electron Device Lett., vol. 21, pp. 76-78, Feb. 2000.
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/40968-
dc.description.abstract金氧半元件的反轉穿隧電流是由界面陷阱產生的電流、塊材陷阱的產生復合電流以及背面接點的擴散電流組合而成。塊材陷阱的產生復合電流和深空乏區寬度成正比。深空乏行為可以在電容對電壓的曲線中發現,深空乏區寬度也可以從中得知。為了消除界面陷阱產生的電流以及擴散電流的影響,利用閘極電壓、空乏區寬度以及反轉穿隧電流的增量來計算,根據結果得知塊材陷阱的產生復合電流主導了反轉穿隧電流,而兩種不一樣的少數載子生存時間也可以得知。其中一種是由靠近矽-二氧化矽接面的表面陷阱產生的少數載子生存時間,另一種則是由遠離矽-二氧化矽接面的基板陷阱產生的少數載子生存時間。高介電常數閘極介電層的品質和其產生深空乏的發生電壓有關係。當深空乏的發生電壓較大時,其累積穿隧電流將會比較小。
氧化鋁和氧化鉿兩種閘極介電層展現出比二氧化矽閘極介電層較佳的阻擋反轉穿隧電流之能力,因此有比較小的反轉穿隧電流。由於次氧化層效應的影響,二氧化矽閘極介電層的飽和電流會隨著介電層厚度的增加而增加。在電流飽和區時,氧化鋁閘極介電層展現出好的阻擋反轉穿隧電流之能力,但是氧化鉿閘極介電層由於其較小的能帶偏移量,導致其展現出不好的阻擋反轉穿隧電流之能力,因此飽和電流隨著等效氧化層厚度的增加卻保持定值。氧化鋁閘極介電層展現出三者中最好的阻擋反轉穿隧電流之能力,因此擁有最大的飽和電壓。
zh_TW
dc.description.abstractThe inversion tunneling current of MOS devices is composed of the generation current due to interface states, the generation-recombination current due to bulk traps, and the diffusion current from back contact. The generation-recombination current due to bulk traps is proportional to the depletion width. The deep-depletion behavior is observed from C-V curves and the deep-depletion width is extracted. According to the calculated results with increments of gate voltage, depletion width and inversion tunneling current, which are designed to eliminate the effects of generation current due to interface states and diffusion current, it was found the inversion tunneling current is dominated by the generation-recombination current due to bulk traps, and two different minority carrier generation lifetimes are acquired. One is the equivalent minority carrier generation lifetime due to surface trap which is close to the interface of Si-SiO2, and the other is the minority carrier generation lifetime due to bulk trap which is far from the interface of Si-SiO2. The quality of high-k gate dielectric is related to the occurred gate voltage of deep-depletion. The accumulation tunneling current would be smaller with higher occurred gate voltage of deep-depletion.
Al2O3 and HfO2 gate dielectrics show better capabilities to block the inversion tunneling current than SiO2 gate dielectrics at a small gate voltage and thus have the smaller inversion tunneling current. The saturation current of SiO2 gate dielectrics increases with increasing EOT due to sub-oxide effect. Al2O3 gate dielectrics show good capabilities to block the tunneling current in the saturation region, but HfO2 gate dielectrics show bad capabilities due to the small conduction band offset of HfO2, and the saturation current keeps the same value with increasing EOT. Al2O3 gate dielectrics have the best capabilities to block the inversion tunneling current and thus have the largest saturation voltage.
en
dc.description.provenanceMade available in DSpace on 2021-06-14T17:09:21Z (GMT). No. of bitstreams: 1
ntu-97-R95943058-1.pdf: 1926439 bytes, checksum: 1a509379747a8a511dc4d41211a6a2bf (MD5)
Previous issue date: 2008
en
dc.description.tableofcontentsAbstract (Chinese)……………………………………..………....I Abstract (English)…………………………………………………III Contents……………………………………..……………......…..V
Table Captions......................................…..VII Figure Captions………………………………………….……….VIII
Chapter 1 Introduction…………………………………………...1
1-1 Motivation of This Work……………………..……..1
1-2 High-k Gate Dielectrics………………………………3
1-3 Equivalent Oxide Thickness Determination of High-k Gate Dielectrics……............................….5
1-4 Experimental Setup………...………………………..9
Chapter 2 Relationship between Deep-depletion and Inversion Tunneling Current for High-k Gate Dielectrics…17
2-1 Theoretical Tunneling Model of MOS Devices……………17
2-2 Determination of Deep-depletion Region Width by Capacitance-voltage Curves……………………………………….20
2-3 Analysis of Generation-recombination Current in Deep-depletion Region….......................................22 2-4 Determination of Oxide Qualities by Deep-depletion Characteristics………....................................29 2-5 Summary………………………………………………………….30
Chapter 3 Comparison of Inversion Tunneling Current Characteristics between SiO2, Al2O3, and HfO2 Gate Dielectrics…………….….............................…..43
3-1 Introduction....………………………………………………43 3-2 Analysis of Inversion Tunneling Current at Low Gate Voltage………….......................................….45 3-3 Analysis of Inversion Tunneling Current in Saturation Region…......................................…………….48
3-3-1 Saturation Current Level…….…………………………48
3-3-2 Saturation Voltage……………………………….……..50
3-4 Summary…………………..…………………………………….51
Chapter 4 Conclusions and Suggestions for Future Work…64
4-1 Conclusions………………………………………………….…64
4-2 Suggestions for Future Work…………………….....…..66
References…………………………………………………….……..67
dc.language.isozh-TW
dc.title金氧半元件中高介電係數閘極介電層之反轉穿隧電流特性分析zh_TW
dc.titleCharacterization of Inversion Tunneling Current for MOS Devices with High-k Gate Dielectricsen
dc.typeThesis
dc.date.schoolyear96-2
dc.description.degree碩士
dc.contributor.oralexamcommittee林致廷(Chih-Ting Lin),郭宇軒(Yu-Hsuan Kuo)
dc.subject.keyword反轉穿隧電流,伸空乏,zh_TW
dc.subject.keywordinversion tunneling current,deep-depletion,en
dc.relation.page70
dc.rights.note有償授權
dc.date.accepted2008-07-29
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept電子工程學研究所zh_TW
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