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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/40597完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | Huan-Chieh Tseng | en |
| dc.contributor.author | 曾煥傑 | zh_TW |
| dc.date.accessioned | 2021-06-14T16:52:40Z | - |
| dc.date.available | 2009-08-04 | |
| dc.date.copyright | 2008-08-04 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-07-29 | |
| dc.identifier.citation | [1] B.Razavi, Principles of Data Conversion System Design. Wiley-IEEE Press, 1995.
[2] Rudy van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters. Kluwer Academic Publishers, 2003. [3] Mikael Gustavsson, J. Jacob Wikner and N. Nick Tan, CMOS Data Converters for Communications. Kluwer Academic Publishers, 2000. [4] S. H. Lewis, H. S. Fetterman, G. F. Gross Jr., R. Ramachandran, and T. R. Viswanathan, “A 10-b 20-Msample/s analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992. [5] T. Cho and P. R. Gray, “A 10 b 20 Msamples/s, 35 mW pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 30, pp. 166–172, Mar. 1995. [6] F. Maloberti, F. Francesconi, P. Malcovati, and O. J. A. P. Nys, “Design considerations on low-voltage low-power data converters,” IEEE Trans. Circuits Syst. I, vol. 42, pp. 853–863, Nov. 1995. [7] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, “Explicit analysis of channel mismatch effects in time-interleaved ADC systems,” IEEE Trans. Circuits Syst. I, vol. 48, pp. 261-271, Mar. 2001. [8] K. Y. Kim, N. Kusayanagi, and A. A. Abidi, “A 10-b, 100-MS/s CMOS A/D converter,” IEEE J. Solid-State Circuits, vol. 32, pp. 302-311, Mar. 1997. [9] D. W. Cline and P. R. Gray, “A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 294-303, Mar. 1996. [10] A. Wada, et al., “A 10 b 20-Msample/s 28 mW CMOS ADC in ASIC process,” Proceedings of the 11th Annual IEEE International ASIC Conference, pp. 57-61, Sept. 1998. [11] A. Wada, et al., “A 10b 50-Msample/s CMOS ADC in ASIC Process,” Proceeding of the 24th European Solid-State Circuits Conference, pp. 252-255, Sept. 1998. [12] K. Tani, et al., “A pipelined ADC macro design for multiple applications,” Proceeding of ASP-DAC 2001, pp. 269-274, Jan. 2001. [13] A. Wada, et al., “A 14mW 10–bit 20–Msample/s ADC in 0.18um CMOS with 61MHz–input,” Proceedings of the 28th Solid-State Circuits Conference, pp. 459-462, Sept. 2002. [14] H. Pan, et al., “A 3.3-V 12-b 50-MS/s A/D Converter in 0.6-μm CMOS with over 80-dB SFDR,” IEEE J. Solid-State Circuits, vol. 35, pp. 1769-1783, Dec. 2000. [15] Imran Ahmed, David A. Johns, “An 11-bit 45MS/s pipelined ADC with rapid calibration of DAC errors in a multi-bit pipeline stage,” 33rd European Solid State Circuits Conference, pp. 147-150, Sept. 2007. [16] L. Sumanen, M. Waltari, and K. Halonen, “A 10-bit 200-MS/s CMOS parallel pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 36, pp. 1048-1055, July 2001. [17] Y.-T. Wang and B. Razavi, “ An 8-bit 150-MHz CMOS A/D converter ,” IEEE J. Solid-State Circuits, vol. 35, no.3, pp. 308-317, March 2000. [18] S.-C. Lee, K.-D. Kim, J.-K. Kwon, J. King, and S.-H. Lee, “ A 10-bit 400-MS/s 160-mW 0.13-μm CMOS dual-channel pipeline ADC without channel mismatch calibration ,” IEEE J. Solid-State Circuits, vol. 41, no.7, pp. 1596-1605, March 2006. [19] Yoshioka M., Kudo M., Gotoh K., Watanabe Y., “A 10b 125MS/s 40mW pipelined ADC in 0.18μm CMOS,” ISSCC Dig. Tech. Papers, pp. 282-284, Feb. 2005. [20] B. Hernes, A. Briskemyr, T. N. Andersen, F. Telstø, T. E. Bonnerud, and Ø. Moldsvor, “A 1.2 V 220MS/s 10b pipeline ADC implemented in 0.13μm digital CMOS,” ISSCC Dig. Tech. Papers, pp. 256-257, Feb. 2004. [21] Behzad Razavi, Design of Analog CMOS Integrated Circuits. New-York: McGraw-Hill, 2001. [22] D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997. [23] P. R. Gray, et al., Analysis and Design of Analog Integrated Circuits. New-York: Wiley, 2001. [24] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May 1999. [25] Byung-Moo Min, P. Kim, F. W. Bowman, III, D. M. Boisvert, and A. J. Aude, “A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol. 38, pp. 2031-2039, Dec. 2003. [26] Jong-Bum Park, Sang-Min Yoo, Se-Won Kim, Young-Jae Cho, and Seung-Hoon Lee, “A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth,” IEEE J. Solid-State Circuits, vol. 39, pp. 1335-1337, Aug. 2004. [27] J. Doernberg, H. Lee, and D. A. Hodges, “Full-speed testing of A/D converters,” IEEE J. Solid-State Circuits, vol. 19, No. 6, pp. 820-827, Dec. 1984. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/40597 | - |
| dc.description.abstract | 本論文闡述一個操作在1.2伏特的十位元雙通道時間交錯式之管線式類比數位轉換器，並以台積電0.13-μm CMOS製程製作。為達到高度的轉換速率，於第一級MDAC內將餘數放大的動作做分解以增加其回授係數。為了減少不匹配所帶來的效應，運算放大器的共用技巧被運用在兩個通道間，以及所提出的時脈產生器被設計用來抑止取樣時間的不匹配。
依據量測的結果，本晶片操作在50MS/s的取樣頻率下，DNL為-0.49/+0.43LSB，INL為-1.05/+0.86LSB，對於1MS/s的信號輸入頻率，在50MS/s的取樣頻率下，SNDR為56.53dB，SFDR為68.38dB，當時脈升至250MS/s時，SNDR與SFDR分別降為37.63dB與41.61dB。在250MS/s的轉換速率下，功率消耗為 106mW。晶片總面積占1.3mm2。 在第一章中，將介紹管線式類比數位轉換器的架構。第二章討論時間交錯式類比數位轉換器系統下其通道間的不匹配所帶來的效應。第三章說明所提出來的新架構，用來增進轉換速度以及減少不匹配的效應。電路細節與模擬結果包含在第四章。第五章呈現量測的設定與量測結果，最後於第六章中對這個電路做總結。 | zh_TW |
| dc.description.abstract | This thesis presents a 1.2V 10-bit CMOS two-channel time-interleaved pipelined ADC in a standard 0.13-μm CMOS process. For high conversion speed, the first stage with divided residue gain is proposed to increase the feedback factor of the MDAC. In order to reduce the mismatch-effects, opamp-sharing technique is applied between two channels, and the proposed clock generator is designed to suppress the sampling-time mismatch.
According to the measurement results, the prototype ADC exhibits a DNL of -0.49/+0.43LSB and an INL of -1.05/+0.86LSB at the sampling rate of 50MS/s. For 1MHz input frequency, the SNDR and SFDR achieve 56.53dB and 68.38dB at 50MS/s. The SNDR and SFDR are reduced to 37.63dB and 41.61dB at 250MS/s for 1MHz input. The power consumption is 106mW at the conversion rate of 250MS/s. The chip with pads occupies 1.3mm2. Chapter 1 introduces the pipelined ADC architecture. Chapter 2 discusses the channel mismatch effects in the time-interleaved ADC system. A proposed architecture to increase conversion speed and to reduce mismatch effects is given in Chapter 3. Detail circuit implementation and simulation result are shown in Chapter 4. Chapter 5 presents the test setup and measurement results. Finally, conclusions are summarized in Chapter 6. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-14T16:52:40Z (GMT). No. of bitstreams: 1 ntu-97-R94943018-1.pdf: 3505690 bytes, checksum: 197d7fd8caa48313fd3219fe230c1fac (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | 致謝………………………………………………………………………I
摘要……………………………………………………………………II Abstract………………………………………………………………III Table of Contents……………………………………………………IV List of Figures………………………………………………………VI List of Tables……………………………………………………VIII Chapter 1 Fundamentals of pipelined A/D converter…………1 1.1 Introduction………………………………………………………1 1.2 Motivation…………………………………………………………1 1.3 Performance metrics……………………………………………2 1.3.1 Differential Nonlinearity (DNL)…………………………2 1.3.2 Integral Nonlinearity (DNL) ………………………………3 1.3.3 Offset Error……………………………………………………3 1.3.4 Gain Error………………………………………………………3 1.3.5 Signal-to-Noise ratio (SNR) ………………………………4 1.3.6 Total Harmonic Distortion (THD) …………………………4 1.3.7 Spurious-Free Dynamic Range (SFDR) ……………………4 1.3.8 Signal-to-Noise and Distortion Ratio (SNDR) …………5 1.3.9 Effective Number of Bits (ENOB) …………………………5 1.4 General pipelined A/D converter……………………………5 1.4.1 1.5-bit per stage architecture for 10-bit pipelined ADC6………………………………………………………………………6 Chapter 2 Time-interleaved Pipelined A/D converter………9 2.1 Introduction………………………………………………………9 2.2 Time-interleaved ADC system…………………………………9 2.3 Channel mismatch effects……………………………………10 2.3.1 Offset mismatch effects……………………………………11 2.3.2 Gain mismatch effects………………………………………12 2.3.3 Clock timing error effects………………………………13 2.3.4 Combined channel mismatch effects………………………14 Chapter 3 Proposed architecture to increase conversion speed and to reduce mismatch effects…………………………16 3.1 Introduction……………………………………………………16 3.2 Speed-limitations of a pipelined ADC without front-end SHA………………………………………………………………………16 3.3 Proposed architecture to increase conversion speed…17 3.4 Proposed architecture to reduce mismatch effects……20 3.4.1 Proposed clock generator…………………………………22 Chapter 4 Circuit implementation and simulation results…………………………………………………………………24 4.1 Introduction……………………………………………………24 4.2 Circuit implementation ………………………………………24 4.2.1 HMDAC……………………………………………………………24 4.2.2 MCKT……………………………………………………………25 4.2.3 Operational amplifier………………………………………25 4.2.4 Bias circuit and CMFB circuit……………………………26 4.2.5 Comparator……………………………………………………27 4.2.5.1 Latch-type comparator……………………………………28 4.2.6 Bootstrap sampling switch…………………………………30 4.2.7 Proposed clock generator…………………………………30 4.3 Simulation results……………………………………………32 4.3.1 Operational amplifier simulation………………………32 4.3.1.1 AC analysis…………………………………………………32 4.3.1.2 DC analysis…………………………………………………32 4.3.2 MDAC transient analysis……………………………………33 4.3.3 MATLAB behavior simulation for gain-mismatch………33 4.3.4 MATLAB behavior simulation for DNL and INL…………35 4.3.5 Full-chip simulation………………………………………35 4.3.6 Summary…………………………………………………………37 Chapter 5 Test setup and measurement results………………38 5.1 Introduction……………………………………………………38 5.2 Test setup………………………………………………………38 5.3 PCB design………………………………………………………39 5.4 Floor plan and layout considerations……………………42 5.5 Experiment results……………………………………………44 5.5.1 Static performance…………………………………………44 5.5.2 Dynamic performance…………………………………………46 5.6 Sources of the performance-degradation…………………48 5.7 Summary……………………………………………………………50 Chapter 6 Conclusions……………………………………………52 Bibliography…………………………………………………………53 | |
| dc.language.iso | en | |
| dc.subject | 時間交錯 | zh_TW |
| dc.subject | 管線式 | zh_TW |
| dc.subject | 類比數位轉換器 | zh_TW |
| dc.subject | time-interleaved | en |
| dc.subject | pipelined | en |
| dc.subject | ADC | en |
| dc.title | 一個操作在1.2伏特之十位元高速管線式類比數位轉換器 | zh_TW |
| dc.title | A 1.2V 10-bit High-Speed Pipelined ADC | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢,陳怡然,蔡宗亨,顧孟愷 | |
| dc.subject.keyword | 管線式,類比數位轉換器,時間交錯, | zh_TW |
| dc.subject.keyword | pipelined,ADC,time-interleaved, | en |
| dc.relation.page | 54 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-07-31 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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