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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳少傑(Sao-Jie Chen) | |
| dc.contributor.author | Cheng Chin Chen | en |
| dc.contributor.author | 陳承錦 | zh_TW |
| dc.date.accessioned | 2021-06-14T16:44:39Z | - |
| dc.date.available | 2013-08-04 | |
| dc.date.copyright | 2008-08-04 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-08-01 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/40315 | - |
| dc.description.abstract | 本篇論文提出一便於擴展之網路晶片路由器硬體架構之設計。此路由器之設計重點有二：其一為減少平均晶片上封包傳輸之延遲時間，其二為依資料傳輸為導向及非固定之設計趨勢提供一可靠性設計之折衷方法。
此論文所提出之路由器設計包含三部分貢獻；第一個部分，路由器使用圖形上二分法配對之想法，並提出一套可維持最大配對可能性的準則下之化簡規則，簡化晶片網路系統上的配置問題。第二個部分，此路由器之設計重新定義了晶片網路上之環境資訊，並提出一資料之可流動性概念，可適用於多種不同路由及仲裁演算法，以便於避免及疏導晶片上之封包傳輸所造成之擁塞。此論文的最後一部分在於，從每一可用單位傳輸資料所需耗費之能量及資料吞吐量下降之統計資訊，以不同的效能折衷比較方法考慮不同的錯誤更正及控制單元，重新考慮重覆傳輸緩衝器之設計。最後，由硬體路由器之實現結果顯示了平均晶片上封包傳輸延遲時間的改進，及在合理的支耗之下提出具可靠性傳輸之設計。 | zh_TW |
| dc.description.abstract | A scalable hardware router design for Network-on-Chip is proposed in this Thesis. The router is designed with an emphasis on reducing average packet latency and on determining reliability design tradeoffs with respect to a communication-centric and non-deterministic design.
The contributions of this router design are threefold. First, the router uses bipartite matching graphs and proposes a set of reductions to reduce the Network-on-Chip allocation problem while retaining the possibility of maximum matching. Next, the router redefines network information for both congestion avoidance and relief purposes by introducing a fluidity concept that can be adapted to many routing and arbitration algorithms. This work also reconsiders the effects of retransmission buffers on energy per useful bit and throughput degradation statistics while presenting a different set of performance tradeoffs geared towards comparing different error correction control schemes. Finally, the hardware router implementation results demonstrate improvements in average packet latency and design for reliability with reasonable increase in overhead. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-14T16:44:39Z (GMT). No. of bitstreams: 1 ntu-97-R95943171-1.pdf: 1479141 bytes, checksum: b9caadd49488c9a16f12860f9c326ced (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | ABSTRACT i
LIST OF FIGURES v LIST OF TABLES vii CHAPTER 1 INTRODUCTION 1 1.1 Communication-Centric Trends 1 1.1.1 System-on-Chip and Computation Demands 2 1.1.2 Bus Architecture and Communication Demands 2 1.2 Non-Determinism Trends 3 1.3 Design Challenges of Network-on-Chips 3 1.3.1 Communication Automation Objective 4 1.3.2 Realization and Terms of Network-on-Chips 4 1.3.3 Different Levels of Network-on-Chip Challenges 6 1.3.3.1 Emphasis on Routing 7 1.3.3.2 Emphasis on Reliability 8 1.4 Problem Formulation and Contributions 8 1.5 Thesis Organization 9 CHAPTER 2 REDUCED FLUID ALLOCATION 11 2.1 Router Primer 12 2.2 Relevant State-of-the-Art Routing Algorithms 13 2.3 NoC Architecture 15 2.4 Motivation from Reducing Packet Latency 15 2.5 Flow Maximization for Allocation Reduction 17 2.5.1 Problem Formulation for Network-on-Chip Allocation 18 2.5.2 Flow Maximization Reduction Technique 20 2.6 Congestion Avoidance and Relief Routing Scheme 22 2.6.1 Fluidity State Transformation 22 2.6.2 Realization on Example Routing Algorithm 24 2.6.3 Realization on Example Arbitration Algorithm 25 2.7 Reduced Fluid Allocation 26 2.8 Routing Setup and Design 28 2.9 Experimental Setup and Results 29 2.9.1 Experimental Results of FMAX 30 2.9.2 Experimental Results of CARRS 33 2.9.3 Experimental Results of Reduced Fluid Allocation Hardware 36 2.10 Conclusion on Reduced Fluid Allocation 39 CHAPTER 3 PERFORMANCE TRADEOFFS FOR NOC RELIABILITY 41 3.1 State-of-the-Art Design Aspects of Reliable NoC Routers 41 3.1.1 Error Control Schemes 42 3.1.2 Error Recovery Mechanisms 43 3.1.3 Derivation of Energy Metrics 44 3.2 Error Control Codes 45 3.3 Energy Formulation with NoC Retransmission Buffer Design 47 3.4 Scaled Performance Metrics for NoC Routers 52 3.5 Experimental Results of ECC with Retransmission Buffers for NoC 52 3.5.1 Standardization of MTTF for ECCs 53 3.5.2 Energy Versus Throughput Results 55 3.6 Conclusion on ECC 56 CHAPTER 4 CONCLUSION 57 REFERENCE 59 | |
| dc.language.iso | en | |
| dc.subject | 網路晶片 | zh_TW |
| dc.subject | 可靠 | zh_TW |
| dc.subject | 路由器 | zh_TW |
| dc.subject | Fault Tolerance | en |
| dc.subject | Router | en |
| dc.subject | Network-on-Chip | en |
| dc.subject | NoC | en |
| dc.title | 一個低耗能且可靠之網路晶片路由器設計 | zh_TW |
| dc.title | Design of a Low-Power Reliable Network-On-Chip Router | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 張耀文(Yao-Wen Chang),熊博安(Pao-Ann Hsiung),蘇培陞(Alan Su) | |
| dc.subject.keyword | 可靠,網路晶片,路由器, | zh_TW |
| dc.subject.keyword | NoC,Network-on-Chip,Router,Fault Tolerance, | en |
| dc.relation.page | 63 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-08-01 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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