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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳良基 | |
dc.contributor.author | Po-Chih Tseng | en |
dc.contributor.author | 曾博志 | zh_TW |
dc.date.accessioned | 2021-06-13T17:24:54Z | - |
dc.date.available | 2006-02-02 | |
dc.date.copyright | 2005-02-02 | |
dc.date.issued | 2005 | |
dc.date.submitted | 2005-01-25 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/39254 | - |
dc.description.abstract | 在本論文,視訊編解碼器系統中的兩個主要功率消耗來源,編解碼器核心與框架緩衝器存取,被三個研究主題所涵蓋。在編解碼器核心方面,具功率感知的有彈性視訊編解碼器系統與具功率感知的MPEG-4視訊編碼器系統的設計與實現分別在第一部分與第二部分中進行研究。而在框架緩衝器存取方面,針對框架緩衝器存取的嵌入式壓縮則在第三部分中做考慮。
具功率感知的視訊編解碼器系統之重要性在第一章中做介紹,而在本論文所採用的低功率設計技巧則在第二章中做說明。第三章(第一部分)討論針對具功率感知的有彈性視訊編解碼器系統的設計方法,而第四章(第一部分)則以離散小波轉換為標的來發展針對具功率感知的有彈性視訊編解碼器系統的特殊功能可重組化硬體加速器。接著,針對具功率感知的MPEG-4視訊編碼器系統的設計方法在第五章(第二部分)中做探討,而幾個具主宰性大量運算的任務之設計則在接下來的三章中做說明,包含了第六章(第二部分)的低功率全域搜尋移動估計處理器,第七章(第二部分)的多重模式內容相關低功率移動估計處理器,以及第八章(第二部分)的內容相關低功率離散餘弦轉換暨量化處理器。然後,第九章(第三部分)考慮針對框架緩衝器存取的低複雜度多重模式嵌入式壓縮引擎。本論文的主要貢獻與未來方向於第十章中做結論。最後,一個針對影像與視訊編碼的硬體架構演進之概括論述則在第十一章中做附錄參考。 | zh_TW |
dc.description.abstract | In this dissertation, two major sources of power dissipation in video codec systems, the codec core and the frame buffer access, are covered by three research topics. For codec core, the design and implementation of power-aware flexible video codec system and power-aware MPEG-4 video encoder system are investigated in Part I and Part II respectively. As for frame buffer access, the embedded compression for frame buffer access is considered in Part III.
The importance of power-aware video codec systems are introduced in Chapter 1. The low-power design techniques to be applied in this dissertation are then reviewed in Chapter 2. Chapter 3 (of Part I) discusses the design approach for power-aware flexible video codec system, and Chapter 4 (of Part I) targets the DWT for the development of function-specific reconfigurable hardware accelerator for power-aware flexible video codec system. The design approach for power-aware MPEG-4 video encoder system is investigated in Chapter 5 (of Part II), and the designs of dominating computation-intensive tasks are described in following three chapters, including the low-power full search ME processor in Chapter 6 (of Part II), the multi-mode content-dependent low-power ME processor in Chapter 7 (of Part II), and the content-dependent low-power DCTQ processor in Chapter 8 (of Part II). Then, in Chapter 9 (of Part III), the low-complexity multi-mode embedded compression engine is considered for frame buffer access. The principal contributions and future directions are concluded in Chapter 10. Finally, an appendix about the survey of advances in hardware architectures for image and video coding is given in Chapter 11. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T17:24:54Z (GMT). No. of bitstreams: 1 ntu-94-D90943009-1.pdf: 4999670 bytes, checksum: 96cacc7a92819b00a63947720ef3f5f3 (MD5) Previous issue date: 2005 | en |
dc.description.tableofcontents | Contents
Abstract xix 1 Introduction 1 1.1 OverviewofVideoCodecSystems . . . . . . . . . . . . . . . . . 1 1.1.1 EvolutionofVideoCodingStandards . . . . . . . . . . . 2 1.1.2 ComputationalComplexityofVideoCoding . . . . . . . 3 1.1.3 CoreTechniquesofVideoCoding . . . . . . . . . . . . . 4 1.1.4 Categories ofVideoCodecSystems . . . . . . . . . . . . 7 1.2 Power Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2.1 FutureTrend of ICDesign . . . . . . . . . . . . . . . . . 8 1.2.2 PowerDissipationandPowerDensity . . . . . . . . . . . 9 1.2.3 MappingofVideoCodecSystems . . . . . . . . . . . . . 10 1.2.4 Sources of Power Dissipation in Video Codec Systems . . 11 1.3 ResearchTopics andDissertationOrganization . . . . . . . . . . 13 1.4 PrincipalContributions . . . . . . . . . . . . . . . . . . . . . . . 14 1.4.1 Power-AwareFlexibleVideoCodecSystem . . . . . . . . 14 1.4.2 Power-Aware MPEG-4 Video Encoder System . . . . . . 15 1.4.3 Embedded Compression for Frame Buffer Access . . . . . 18 1.4.4 OtherContributions . . . . . . . . . . . . . . . . . . . . 18 i ii 2 Low-Power Design Techniques 21 2.1 MinimizationofPowerDissipation . . . . . . . . . . . . . . . . . 21 2.1.1 Sources ofPowerDissipation . . . . . . . . . . . . . . . 21 2.1.2 Components of Power Dissipation . . . . . . . . . . . . . 22 2.1.3 LevelsofLow-PowerDesignTechniques . . . . . . . . . 24 2.1.4 MinimizationofPowerDissipation . . . . . . . . . . . . 24 2.2 System-LevelLow-PowerDesignTechnique . . . . . . . . . . . . 26 2.2.1 Power Efficiency and Flexibility Tradeoff of Modules . . . 27 2.2.2 Power Efficiency and Flexibility Tradeoff of Interconnect . 27 2.3 Module-Level Low-Power Design Techniques . . . . . . . . . . . 28 2.3.1 Algorithm, Architecture, and Logic Levels Co-Design . . 29 2.3.2 Content-Dependent Variable Workload Processing . . . . 30 2.4 Power-AwareSystems . . . . . . . . . . . . . . . . . . . . . . . 32 I Power-Aware Flexible Video Codec System 35 3 Design Approach for Power-Aware Flexible Video Codec System 37 3.1 ReviewofFlexibleVideoSystemPlatforms . . . . . . . . . . . . 38 3.2 DesignApproach . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.2.1 System Partitioning . . . . . . . . . . . . . . . . . . . . . 40 3.2.2 Function-Specific Reconfigurable Hardware Accelerator . 41 4 Reconfigurable DWT Processor 43 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2 LiftingScheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.3 SystematicDesignMethod . . . . . . . . . . . . . . . . . . . . . 50 4.3.1 SpecificLiftingFactorization . . . . . . . . . . . . . . . 51 4.3.2 DependenceGraphFormation . . . . . . . . . . . . . . . 53 iii 4.3.3 SystolicArrayMappingandPipelining . . . . . . . . . . 54 4.3.4 CaseStudies . . . . . . . . . . . . . . . . . . . . . . . . 56 4.4 ReconfigurableDWTProcessorArchitecture . . . . . . . . . . . 59 4.4.1 ArchitectureOverview . . . . . . . . . . . . . . . . . . . 59 4.4.2 ReconfigurableDWTPEArray . . . . . . . . . . . . . . 60 4.4.3 ReconfigurableWPTAG . . . . . . . . . . . . . . . . . . 63 4.5 ImplementationandPerformanceEvaluation. . . . . . . . . . . . 63 4.5.1 Chip Implementation . . . . . . . . . . . . . . . . . . . . 63 4.5.2 PerformanceEvaluation . . . . . . . . . . . . . . . . . . 67 4.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 II Power-Aware MPEG-4 Video Encoder System 71 5 Design Approach for Power-Aware MPEG-4 Video Encoder System 73 5.1 ReviewofPriorArts . . . . . . . . . . . . . . . . . . . . . . . . 74 5.2 DesignApproach . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2.1 System Partitioning . . . . . . . . . . . . . . . . . . . . . 76 5.2.2 Bottom-UpApproach . . . . . . . . . . . . . . . . . . . . 77 6 Low-Power Full Search ME Processor 79 6.1 Introudction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2 ExistingAlgorithmsandArchitectures . . . . . . . . . . . . . . . 80 6.2.1 ExistingAlgorithms forFullSearchME . . . . . . . . . . 81 6.2.2 ExistingArchitectures forFullSearchME. . . . . . . . . 84 6.3 Proposed Low-Power Full Search ME Processor . . . . . . . . . . 89 6.3.1 Increasing Parallelism in Sub-Tree Architecture . . . . . . 89 6.3.2 Proposed Parallel Tree Architecture . . . . . . . . . . . . 92 6.3.3 Low-Power Operation by Exploiting the PDE . . . . . . . 94 iv 6.3.4 DifferentParallelisms inParallelTree . . . . . . . . . . . 98 6.3.5 Architecture of Low-Power Full Search ME Processor . . 100 6.3.6 ComparisonwithOtherArchitectures . . . . . . . . . . . 106 6.4 ImplementationandPerformanceEvaluation. . . . . . . . . . . . 113 6.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7 Multi-Mode Content-Dependent Low-Power ME Processor 121 7.1 Introudction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.2 ExistingAlgorithms forFastSearchME . . . . . . . . . . . . . . 122 7.2.1 ThreeStepSearch . . . . . . . . . . . . . . . . . . . . . 123 7.2.2 FourStepSearch . . . . . . . . . . . . . . . . . . . . . . 123 7.2.3 DiamondSearch . . . . . . . . . . . . . . . . . . . . . . 124 7.2.4 EnhancedFourStepSearch . . . . . . . . . . . . . . . . 125 7.2.5 ComparisonofFastSearchAlgorithms . . . . . . . . . . 125 7.3 Content-Dependent Diversity-Based Motion Estimation Algorithm 126 7.3.1 TheVarianceofMotionVectors . . . . . . . . . . . . . . 128 7.3.2 TheAccuracy ofPredictedMotionVectors . . . . . . . . 131 7.3.3 Content-Dependent Diversity-Based Motion EstimationAlgorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 7.3.4 SimulationResults . . . . . . . . . . . . . . . . . . . . . 142 7.4 Power-Aware Reconfigurable Motion Estimation Architecture . . 148 7.4.1 The Similarity between Different Algorithms . . . . . . . 148 7.4.2 BlockDiagramof theArchitectue . . . . . . . . . . . . . 149 7.4.3 Flow Chart of Multi-Mode Content-Dependent Low-Power MEProcessor . . . . . . . . . . . . . . . . . . . . . . . . 156 7.4.4 ComparisonwithOtherArchitectures . . . . . . . . . . . 156 7.5 ImplementationandPerformanceEvaluation. . . . . . . . . . . . 158 7.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 v 8 Content-Dependent Low-Power DCTQ Processor 165 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 8.2 ExistingAlgorithmsandArchitectures . . . . . . . . . . . . . . . 169 8.2.1 ExistingContent-DependentAlgorithms . . . . . . . . . . 169 8.2.2 BasicArchitectures . . . . . . . . . . . . . . . . . . . . . 171 8.2.3 ExistingContent-DependentArchitectures . . . . . . . . 180 8.3 Proposed Content-Dependent DCT and IDCT Designs . . . . . . 184 8.3.1 Proposed Content-Dependent DCT Design . . . . . . . . 184 8.3.2 Proposed Content-Dependent IDCT Design . . . . . . . . 189 8.4 ImplementationandPerformanceEvaluation. . . . . . . . . . . . 191 8.4.1 Gate-Level Implementation . . . . . . . . . . . . . . . . 191 8.4.2 PerformanceEvaluation . . . . . . . . . . . . . . . . . . 195 8.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 III Embedded Compression for Frame Buffer Access 201 9 Low-Complexity Multi-Mode Embedded Compression Engine 203 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 9.2 DesignGoals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 9.3 Proposed Tree-Pipelined SPIHT Scheduling for Multi-Mode EmbeddedCompression . . . . . . . . . . . . . . . . . . . . . . . . 207 9.3.1 OverviewofSPIHT . . . . . . . . . . . . . . . . . . . . 208 9.3.2 Proposed Tree-Pipelined SPIHT Scheduling . . . . . . . . 209 9.4 Proposed Architecture for Tree-Pipelined SPIHT Scheduling . . . 211 9.4.1 Proposed Scheme for Tree-Pipelined Multi-LevelDWT/IDWT212 9.4.2 Proposed Architecture for 8×8 SPIHT Engine . . . . . . 214 9.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 vi 10 Conclusion 217 10.1 PrincipalContributions . . . . . . . . . . . . . . . . . . . . . . . 217 10.1.1 Power-AwareFlexibleVideoCodecSystem . . . . . . . . 217 10.1.2 Power-Aware MPEG-4 Video Encoder System . . . . . . 218 10.1.3 Embedded Compression for Frame Buffer Access . . . . . 221 10.1.4 OtherContributions . . . . . . . . . . . . . . . . . . . . 221 10.2 FutureDirections . . . . . . . . . . . . . . . . . . . . . . . . . . 222 11 [Appendix] Advances inHardware Architectures for Image and Video Coding – A Survey 223 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 11.2 Fundamentals of Hardware Architectures . . . . . . . . . . . . . 225 11.3 HardwareArchitectures forMPEG-4 . . . . . . . . . . . . . . . . 229 11.3.1 Algorithm Analysis and Architecture Exploration . . . . . 230 11.3.2 Module Architectures . . . . . . . . . . . . . . . . . . . . 231 11.3.3 SystemArchitectures . . . . . . . . . . . . . . . . . . . . 235 11.4 Hardware Architectures for JPEG 2000 . . . . . . . . . . . . . . 239 11.4.1 Algorithm Analysis and Architecture Exploration . . . . . 239 11.4.2 Module Architectures . . . . . . . . . . . . . . . . . . . . 242 11.4.3 SystemArchitectures . . . . . . . . . . . . . . . . . . . . 246 11.5 FurtherPerspectives . . . . . . . . . . . . . . . . . . . . . . . . . 251 | |
dc.language.iso | en | |
dc.title | 具功率感知的視訊編解碼器系統之設計與實現 | zh_TW |
dc.title | Design and Implementation of Power-Aware Video Codec Systems | en |
dc.type | Thesis | |
dc.date.schoolyear | 93-1 | |
dc.description.degree | 博士 | |
dc.contributor.oralexamcommittee | 賴永康,楊佳玲,杭學鳴,楊家輝,吳安宇,陳永昌,李鎮宜 | |
dc.subject.keyword | 設計,視訊編解碼器,實現,功率,視訊編解碼器系統,具功率感知, | zh_TW |
dc.subject.keyword | Video Codec System,Power-Aware,Design,Implementation,Video Codec,Power, | en |
dc.relation.page | 279 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2005-01-26 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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