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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳中平 | |
| dc.contributor.author | Han-Sung Kuo | en |
| dc.contributor.author | 郭漢松 | zh_TW |
| dc.date.accessioned | 2021-06-13T17:24:12Z | - |
| dc.date.available | 2006-02-02 | |
| dc.date.copyright | 2005-02-02 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-01-27 | |
| dc.identifier.citation | [1] Farzan K., Johns D.A., “A power-efficient architecture for high-speed D/A converters”, Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, Volume: 1, 25-28 May 2003 Pages: I-897 - I-900 vol.1.
[2] Mikael Gustavsson, J. Jacob Wikner, Nianxiong Nick Tan, “CMOS Data converters for communications”, Kluwer Academic Publishers, Boston, 2000. [3] Yijun Zho, Jiren Yuan, “An 8-Bit 100-MHz low glitch interpolation DAC”, Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, Volume: 4, 6-9 May 2001, Pages: 116 - 119 vol. 4. [4] P. endriks, “Specifying communications DACs”, Spectrum, IEEE, Volume: 34, Issue: 7, July 1997 Pages: 58–69. [5] D.A. Johns, K. Martin, “Analog Integrated Circuit Design”, John Wiley & Sons, Inc. 1997. ISBN: 0-471-1448-7. [6] B. Razavi, “Principles of Data Converter System Design”, New York, IEEE Press, 1995. [7] Miki T., Nakamura Y., Nakaya M., Asai S., Akasaka Y., Horiba Y., “An 80-MHz 8-bit CMOS D/A converter”, Solid-State Circuits, IEEE Journal of, Volume: 21, Issue: 6, Dec 1986 Pages: 983–988. [8] Chi-Hung Lin, Bult K., “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2”, Solid-State Circuits, IEEE Journal of Volume: 33, Issue: 12, Dec. 1998 Pages: 1948 – 1958. [9] Yonghua Cong, Geiger R.L., “Formulation of INL and DNL yield estimation in current-steering D/A converters”, Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, Volume: 3, 26-29 May 2002 Pages: III-149-III-152 vol.3 [10] Van den Bosch, A., Steyaert M., Sansen W., “An accurate statistical yield model for CMOS current-steering D/A converters”, Circuits and Systems, ISCAS 2000 Geneva. The 2000 IEEE International Symposium on, Volume: 4, 28-31 May 2000 Pages: 105-108 vol.4. [11] Kadaba R. Lakshmikumar, Robert A. Hadaway, Miles A. Copeland, “Characterization and Modeling of mismatch in MOS Transistors for Precision Analog Design”, Solid-State Circuits, IEEE Journal of Volume: SC-21, NO. 6, December 1986. [12] van den Bosch A., Borremans M.A.F., Steyaer, M.S.J., Sansen W., “A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter”, Solid-State Circuits, IEEE Journal of Volume: 36, Issue: 3, March 2001, Pages: 315 – 324. [13] Nakamura Y., Miki T., Maeda A., Kondoh H., Yazawa N., “A 10-b 70-MS/s CMOS D/A converter”, Solid-State Circuits, IEEE Journal of Volume: 26, Issue: 4, April 1991 Pages: 637 – 642. [14] Hyuen-Hee Bae, Jin-Sik Yoon, Myung-Jin Lee, Eun-Seok Shin, Seung-Hoon Lee, “A 3 V 12b 100 MS/s CMOS D/A converter for high-speed system applications”, Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, Volume: 1, 25-28 May 2003, Pages: I-869 - I-872 vol.1. [15] Ionascu C., Burdia D., “Design and implementation of video DAC in 0.13um CMOS technology”, Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on, Volume: 2, 10-11 July 2003 Pages: 381-384 vol.2. [16] Sung Yong Park, Hyun Ho Cho, Kwang Sub Yoon, “A 3.3 V-110 MHz 10-bit CMOS current-mode DAC”, ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on, 6-8 Aug. 2002 Pages:173-176. [17] Vandenbussch J., Van der Plas G., Daems W., Van den Bosc A., Gielen G., Steyaert M., Sansen W., “Systematic design of high-accuracy current-steering D/A converter macrocells for integrated VLSI systems”, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], Volume: 48, Issue: 3, March 2001 Pages: 300 – 309. [18] Bugeja A.R., Song B.S., Rakers P.L., Gillig S.F., “A 14-b, 100-MS/s CMOS DAC designed for spectral performance”, Solid-State Circuits, IEEE Journal of, Volume: 34, Issue: 12, Dec. 1999 Pages: 1719–1732. [19] Van den Bosc, A., Borremans M., Vandenbussche J., Van der Plas G., Marques A., Bastos J., Steyaert M., Gielen G., Sansen W., “12 bit 200 MHz low glitch CMOS D/A converter”, Custom Integrated Circuits Conference, 1998., Proceedings of the IEEE 1998, 11-14 May 1998, Pages: 249 – 252. [20] Sumane L., Waltari M., Halonen K., “A 10-bit high-speed low-power CMOS D/A converter in 0.2 mm2“, Electronics, Circuits and Systems, 1998 IEEE International Conference on, Volume: 1, 7-10 Sept. 1998 Pages: 15 - 18 vol.1. [21] Ki-Hong Ryu, Kwang Sub Yoon, Hong Ki Min, “Design of a 3.3 V 12 bit CMOS D/A converter with a high linearity”, Circuits and Systems, 1998 Midwest Symposium on, 9-12 Aug. 1998 Pages: 538 – 541. [22] Bastos J.; Steyaert M., Sansen W., “A high yield 12-bit 250-MS/s CMOS D/A converter”, Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 5-8 May 1996 Pages: 431 - 434 [23] Tien-Yu Wu, Ching-Tsing Jih, Jueh-Chi Chen, Chung-Yu Wu, “A low glitch 10-bit 75-MHz CMOS video D/A converter”, Solid-State Circuits, IEEE Journal of Volume: 30, Issue: 1, Jan. 1995 Pages: 68–72. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/39194 | - |
| dc.description.abstract | 現今無線通訊設備之需求嚴苛。而大部分之訊號皆可在數位電路上完成，但資訊需轉換成類比訊號，因此較難建立的部分在於類比-數位轉換器及數位-類比轉換器。
在這篇論文裡，描述用於802.11a之10位元250MSample/s current-steering數位-類比轉換器，並加上內插功能於頻率應用上。對於802.11a發射機之規格而言，頻道之頻寬是20MHz。因此數位-類比轉換器之輸入頻寬被訂於20MHz。用於調變之64 QAM須使用8~10位元。所以，輸入位元數可訂於10位元來增加解析度。 採用內插功能是使濾波器規格之訂定較為寬鬆。而特殊之佈局技術及交換式電流源電路可改善電流源矩陣之效能及尺寸。使用防突波電路是要消除數位資料分同步效應。為了增加數位-類比轉換器之精確度，非線性與線性之效應可被預估在晶片下線之前。 內插式數位-類比轉換器使用Mix Mode 0.35μm CMOS技術且功率消耗60.2mW。顆粒面積為2.25mm2。 | zh_TW |
| dc.description.abstract | The requirements on today’s wireless communications equipment are very hard. Most of the signal processing is done in the digital domain, but the information has to be transferred with analog signals, and therefore analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are crucial building blocks.
In this thesis, a 10-bit 250MSample/s current-steering DAC is presented for 802.11a transceiver, with interpolation function for frequency domain applications. For 802.11a transceiver standard, the channel bandwidth is 20MHz. Thus the input bandwidth of DAC can be defined 20MHz. 64 QAM which be used modulation has to need 8~10 bit. So, the input bit number is defined 10 bit to increate the resolution. Using interpolation function is to release the specification of filter in the transceiver. The special technique of layout and circuit of switch current source are employed to improve the performances and size of the current source matrix. Deglitch circuit is used to eliminate the digital data asynchronous effects. In order to increate accuracy of the DAC, nonlinearity and linearity effects can be estimated before to tape out the chip. This interpolation DAC uses mix mode 0.35μm CMOS technology and power consumption is 60.2mW. The die area is 2.25mm2. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T17:24:12Z (GMT). No. of bitstreams: 1 ntu-94-R91943091-1.pdf: 36521095 bytes, checksum: 366efb103f0ac48ffacada58e644d49b (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | Chapter 1 Introduction 1
1.1 Motivation ………………………………………………1 1.2 Organization ……………………………………………2 Chapter 2 Architectures of DAC 3 2.1 Fundamentals ……………………………………………3 2.2 Quantization ……………………………………………4 2.3 Static Performance ……………………………………6 2.4 Dynamic Performance……………………………………7 2.5 Frequency Domain Performance………………………11 2.6 Performance Limitations ……………………………12 2.7 Voltage Division Architecture ……………………14 2.8 Current Division Architecture ……………………18 2.9 Charge Division Architecture………………………22 2.10 Resistor Based Architecture ………………………28 Chapter 3 Estimation of Performance in Current-Steering DAC 32 3.1 Major Error Sources in Current-steering DACs…32 3.2 Output Resistance Variation for SNDR……………33 3.3 Current Source Mismatch ……………………………34 3.4 Influence of Circuit Noise…………………………36 3.5 INL_yield Estimation in Current-Steering DAC…38 Chapter 4 Design of Interpolation DAC 46 4.1 Oversampling and Interpolation for DAC…………46 4.2 Architecture of Interpolation DAC ………………48 4.3 Preamp circuit and TSPC DFF ………………………49 4.4 Digital circuit and Deglitching circuit ………52 4.5 Implementation of Switch Current Cell …………53 4.6 Output Circuit…………………………………………58 4.7 Layout and Post Simulation…………………………59 4.8 Measured Results………………………………………64 4.9 Conclusionsv……………………………………………71 References 72 | |
| dc.language.iso | zh-TW | |
| dc.subject | 內插 | zh_TW |
| dc.subject | 發射機 | zh_TW |
| dc.subject | 防突波 | zh_TW |
| dc.subject | 濾波器 | zh_TW |
| dc.subject | Transceiver Interpolation 64QAM Deglitch | en |
| dc.title | 10位元 250MSample/s 內插式數位類比轉換器 | zh_TW |
| dc.title | 10 Bit 250MSample/s Interpolation Digital to Analog Converter | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃天偉,盧信嘉 | |
| dc.subject.keyword | 發射機,防突波,濾波器,內插, | zh_TW |
| dc.subject.keyword | Transceiver Interpolation 64QAM Deglitch, | en |
| dc.relation.page | 74 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2005-01-27 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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| ntu-94-1.pdf 未授權公開取用 | 35.67 MB | Adobe PDF |
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