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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 吳肇欣(Chao-Hsin Wu) | |
dc.contributor.author | Shuo Hwai | en |
dc.contributor.author | 懷碩 | zh_TW |
dc.date.accessioned | 2021-05-13T08:38:14Z | - |
dc.date.available | 2016-07-26 | |
dc.date.available | 2021-05-13T08:38:14Z | - |
dc.date.copyright | 2016-07-26 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-07-14 | |
dc.identifier.citation | [1] International Technology Roadmap for Semiconductors 2013 Edition Executive Summary, p. 17
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/3900 | - |
dc.description.abstract | 本篇論文著重在於二維材料中石墨烯及二硫化鉬免除轉印製程的上閘極電晶體的製作,由於氧化層的成長對於上閘極電晶體的特性極為重要,所以我們先最佳化了以原子層沉積技術成長高介電係數三氧化二鋁於石墨烯的成長參數,接著將其應用至二硫化鉬上閘極電晶體。此外,本論文也藉由下閘極電晶體開始,最終製成雙閘極結構的電晶體來探討氧化層對於下閘極電晶體的影響以及比較上閘極及下閘極電晶體之元件特性差別。
本論文可分為兩大部份,第一部分為免轉印石墨烯上閘極電晶體的製作,首先藉由不同成長參數的探討找出最佳原子層沉積條件,其中使用最佳條件製得的上閘極石墨烯電晶體具有15.4 cm2V-1s-1之電洞遷移率以及13.6 cm2V-1s-1之電子遷移率,此外其電流滯後現象少於2 V以及擁有在0 V之狄拉克點。雙閘極電晶體亦製作用來比較上閘極與下閘極電晶體的差異,其中我們發現下閘極電晶體在原子層沉積氧化層後,元件特性大幅提升,電洞遷移率由660 cm2V-1s-1提升至993 cm2V-1s-1而電子遷移率也由469 cm2V-1s-1 提升至911 cm2V-1s-1,推測應是肇因於此氧化層有保護石墨烯免於環境污染的功效,而當雙閘極電晶體的上閘極電極製作上去後,上及下閘極之元件特性皆變差,推測氧化層因為電子束蒸鍍之熱能而損壞,以及氧化層中的氧原子藉由熱能與石墨烯形成氧化石墨烯而造成載子遷移率下降。 第二部分中我們將原子層沉積氧化層於石墨烯上的技術應用至二硫化鉬並且成功製造出上閘極二硫化鉬電晶體,其電子遷移率為0.13 cm2V-1s-1。在二硫化鉬薄膜轉印至二氧化矽/矽基板後,二硫化鉬雙閘極電晶體亦被製作用來比較上下閘極的差異。下閘極電晶體在原子層沉積氧化層後,元件特性大幅提升的現象亦被觀察到,電子遷移率由0.0097 cm2V-1s-1提升至0.045 cm2V-1s-1,接著進行上閘極金屬蒸鍍製程做成雙閘極電晶體,發現下閘極電晶體的電子遷移率顯著上升,我們推測乃因鍍金屬時的熱能使得氧化層中的氧原子與二硫化鉬形成導電度較佳的氧化鉬,因而提升載子遷移律。由載子遷移率可觀察需轉印之上閘極二硫化鉬電晶體的部分較免轉印的二硫化鉬電晶體低,由此可知免轉印電晶體可免於轉印時造成的污染而有著更加的電晶體表現。 | zh_TW |
dc.description.abstract | In this thesis, we focus on the fabrication of transferring-free top-gated transistors using two-dimensional material: graphene and MoS2 as the channel. The growth of top-gate dielectric is critical in the fabrication process. Therefore, we have optimized the growth conditions of high-k Al2O3 on graphene by the atomic layer deposition technique (ALD). Then, this technique is also applied to top-gated MoS2 transistors. Additionally, a sequential investigation of dual-gated transistor is carried out to investigate the influence of the top dielectric layer to bottom-gated transistors and the difference between top- and bottom-gated transistors.
This thesis is divided into two parts. The first part is the fabrication of transferring-free graphene transistors. The ALD growth recipe is first investigated. The best recipe is applied to fabricate the transferring-free graphene transistor. The device shows an hole mobility of 15.4 cm2V-1s-1 and electron mobility of 13.6 cm2V-1s-1 with a hysteresis less than 2 V and a Dirac point at 0 V. Then, the dual-gated graphene transistor is made to investigate the difference between top- and bottom-gated transistors. The performance enhancement is found right after the oxide deposition on bottom-gated transistor, showing the increment of hole mobility 660 cm2V-1s-1to 993 cm2V-1s-1from and electron mobility from 469 cm2V-1s-1 to 911 cm2V-1s-1. We believe that the oxide layer acts as a passivation layer to prevent contaminations from the environment to the graphene channel. However, after the top-gate metal is deposited, the performance of both top- and bottom- gated transistors are degraded. We believe that the heat introduced during e-beam evaporation is responsible for the degradation, which enables graphene to interact with the oxygen atom of the Al2O3 layer and form graphene oxide. In this case, lower conductivity than graphene and thus decreased mobility are observed for the device. In the second part, the oxide growth technique using ALD is applied to the fabrication of transferring-free top-gated MoS2 transistor. The electron mobility is 0.13 cm2V-1s-1. Dual-gated MoS2 structure is also made to compare top-gated transistor with bottom-gated transistor after the MoS2 film transferred to a SiO2/Si substrate. The performance enhancement of bottom-gated transistor is also observed after the oxide is grown on bottom-gated transistor, the mobility values increase from 0.0097 to 0.045 cm2V-1s-1. However, after the top-gate metal is deposited, the performance of bottom-gated transistors is even further improved. We believe that the heat introduced during the metal deposition is responsible for the improved performance, which would enable MoS2 to interact with the oxygen atom of the Al2O3 layer and form Mo oxides. The higher conductivity of the material will induce the mobility value enhancement. On the other hand, the top-gated transistor has worse performance comparing with transferring-free top-gated transistor. This difference further proves the advantage of transferring-free process that avoids the contamination during transfer process. | en |
dc.description.provenance | Made available in DSpace on 2021-05-13T08:38:14Z (GMT). No. of bitstreams: 1 ntu-105-R03941014-1.pdf: 6659072 bytes, checksum: 8d2f5bac90fbb12508b929bb081f9b2b (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | 口試委員審定書 I
Verification letter from the Oral Examination Committee II 致謝 III 摘要 IV Abstract VI Table of Contents IX List of Figures XII List of Tables XVII Chaper 1. Introduction 1 1.1. The Upcoming End of Scaling of Silicon MOSFETs 1 1.2. Development and Rationale of Two-dimensional Materials 3 1.3. Fundamentals of Two-dimensional Materials 5 1.3.1. Basics of Graphene 5 1.3.2. Basics of MoS2 12 1.4. The Organization of the Thesis 15 Chaper 2. Introduction of Experimental Instruments 18 2.1. Material Growth and Device Fabrication Instruments 18 2.1.1. Low Pressure Chemical Vapor Deposition System (LPCVD) 18 2.1.2. Transition Metal Deposition System: Radio-frequency (RF) Sputtering Deposition System 22 2.1.3. Transition Metal Sulfurization System: 24 2.1.4. Electron beam Evaporation Physical Vapor Deposition System (EBPVD) 26 2.1.5. Reactive-Ion Etching (RIE) System 28 2.1.6. Atomic Layer Deposition (ALD) System 28 2.2. Characterization Instruments 32 2.2.1. High Resolution Confocal Raman Spectroscopy 32 2.2.2. Transmission Electron Microscope (TEM) 34 2.2.3. Atomic Force Microscope (AFM) 34 Chaper 3. Top-gated Graphene Transistors Fabricated on Graphene Grown Directly on Sapphire Substrates 38 3.1. The Fabrication Procedure of Top-gated Graphene Transistors 38 3.1.1. The Growth of Graphene Films Directly on Sapphire Substrates 39 3.1.2. The Device Fabrication Procedure of the Graphene Transistors 41 3.2. Growth Optimization of Al2O3 Dielectric Layers on Graphene and Device Performances of Top-gated Graphene Transistors 41 3.2.1. Device Performances of Top-gated Graphene Transistors 55 3.3. Comparison of Graphene Transistors between Top- and Bottom- gated Structure 55 3.4. Conclusions 67 Chaper 4. Top-gated MoS2 Transistors Fabricated by Sulfurization of Pre-deposited Mo Films 68 4.1. The Fabrication Procedure of Top-gated MoS2 Transistors 68 4.1.1. The Growth of MoS2 Film by Using Sulfurization of Pre-deposited Mo Films 68 4.1.2. The Device Fabrication Procedure of Top-gated MoS2 Transistors 71 4.2. The Device Performances of Top-gated MoS2 Transistors 71 4.3. Comparison of Top- and Bottom- gated MoS2 Transistors 75 4.4. Conclusions 82 Chaper 5. Conclusion and Future Work 86 5.1. Conclusion 86 5.2. Future Work 87 References 89 | |
dc.language.iso | en | |
dc.title | 利用原子層沉積技術成長氧化層並製作免轉印上閘極石墨烯及二硫化鉬電晶體 | zh_TW |
dc.title | Graphene and MoS2 Transferring-Free Top-Gated Transistors with Dielectric Layers Fabricated by Using the Atomic Layer Deposition | en |
dc.type | Thesis | |
dc.date.schoolyear | 104-2 | |
dc.description.degree | 碩士 | |
dc.contributor.coadvisor | 林時彥(Shih-Yen Lin) | |
dc.contributor.oralexamcommittee | 李嗣涔(Si-Chen Lee),張書維(Shu-Wei Chang) | |
dc.subject.keyword | 二維材料,石墨烯,二硫化鉬,場效電晶體,原子層沉積,免轉印, | zh_TW |
dc.subject.keyword | Two-dimensional (2D) material,Graphene,MoS2,Metal-oxide-semiconductor field-effect transistor (MOSFET),transferring-free, | en |
dc.relation.page | 93 | |
dc.identifier.doi | 10.6342/NTU201600721 | |
dc.rights.note | 同意授權(全球公開) | |
dc.date.accepted | 2016-07-14 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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