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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 郭正邦 | |
dc.contributor.author | Yu-Sheng Lin | en |
dc.contributor.author | 林育生 | zh_TW |
dc.date.accessioned | 2021-06-13T16:48:30Z | - |
dc.date.available | 2005-07-04 | |
dc.date.copyright | 2005-07-04 | |
dc.date.issued | 2005 | |
dc.date.submitted | 2005-06-27 | |
dc.identifier.citation | 第1章
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Manchanda, “Gate Capacitance Attenuation in MOS Devices with Thin Gate Dielectrics,” IEEE Electron Device Letters, Vol. 17, NO. 11, November 1996. [2.2] B. Cheng, M. Cao, R. Rao, A. Inani, P. V. Voorde, W. M. Greene, Johannes M. C. Stork, Z. Yu, Peter M. Zeitzoff, and Jason C. S. Woo, ”The Impact of High-k Gate Dielectrics and Metal Gate Electrodes on Sub-100 nm MOSFET’s, “ IEEE Trans. Electron Devices, pp. 1537-1544, July 1999. [2.3] N. R. Mohapatra, M. P. Desai, S. G. Narendra, and V. R. Rao, “Modeling of Parasitic Capacitances in Deep Submicrometer Conventional and High-K Dielectric MOS Transistors,” IEEE Trans. Electron Devices, Vol. 50, NO. 4, pp. 959-966, April 2003. 第3章 [3.1] C. Hobbs, H. Tseng, K. Reid, B. Taylor, L. Dip, L. Hebert, R. Garcia, R.Hegde, J. Grant, D. Gilmer, A. Franke, V. Dhandapani, M. Azrak, L. Prabhu, R. Rai, S. Bagchi, J. Conner, S. Backer, F. Dumbuya, B. Nguyen, and P. Tobin, “80nm Poly-Si Gate CMOS with HfO2 Gate Dielectric, “ IEDM Digest, pp. 651-654, 2002. [3.2] K. G. Anil, A. Veloso, S. Kubicek, T. Schram, E. Augendre, J. F. de Marneffe, K. Devriendt, A. Lauwers, S. Brus, K. Henson, and S. Biesemans, “Demonstration of Fully Ni-Silicided Metal Gates on HfO2 Based High-K Gate Dielectrics as a Candidate for Low Power Applications, “Digest of Symp. VLSI Technology, pp. 190-191, 2004. [3.3] A. Vandooren, S. Egley, M. Zavalal, T. Stephens, L. Mathew, M. Rossow, A. Thean, A. Barr, Z. Shi, T. White, D. Pham, J. Conner, L. Prabhu, D. Triyoso, J. Schaeffer, D. Roan, B. Y. Nguyen, M. Orlowski, J. Mogab, “50-nm FD SOI CMOS Technology with HfO2 Gate Dielectric, “ IEEE Trans. Nano-technology, pp. 324-328, Dec. 2003. [3.4] A. Vandooren, A. Barr, L. Mathew, T. R. White, S. Egley, D. Pham, M. Zavala, S. Samavedam, J. Schaeffer, J. Conner, B.-Y. Nguyen, B. E. White, Jr., M. K. Orlowski, and J. Mogab, “Fully-Depleted SOI Devices with TaSiN Gate, HfO2 Gate Dielectric, and Elevated Source/Drain Extensions,’’ IEEE Electron Devices Letters, Vol. 24, No. 5, pp. 342-344, May 2003. [3.5] D. L. Kencke, W. Chen, H. Wang, S. Mudanai, Q. Ouyang, A. Tasch, and S. Banerjee, “ Source-side Barrier Effects with Very High-K Dielectrics in 50nm Si MOSFETs,” Device Research Conf. Digest, pp. 22-23, June 1999. [3.6] N. R. Mohapatra, M. P. Desai, S. G. Narendra, and V. R. Rao, “Modeling of Parasitic Capacitances in Deep Submicrometer Conventional and High-K Dielectric MOS Transistors,” IEEE Trans. Electron Devices, Vol. 50, NO. 4, pp. 959-966, April 2003. [3.7] N. R. Mohapatra, M. P. Desai, S. G. Narendra, and V. R. Rao, “The Effect of High-K Gate Dielectrics on Deep Submicrometer CMOS Device and Circuit Performance,” IEEE Trans. Electron Devices, Vol. 49, NO. 5, pp. 826-831, May 2002. [3.8] C. H. Choi, J. S. Goo, T. Y. Oh, Z. Yu, R. W. Dutton, A. Bayoumi, M. Cao, P. V. voorde, D. Vook, C. H. Diaz, “MOS C-V Characterization of Ultrathin Gate Oxide Thickness (1.3-1.8nm)”, IEEE Elec. Dev. Letters, Vol 20, NO. 6, pp. 292-294, June 1999. [3.9] C. H. Choi, Y. Wu, J. S. Goo, Z. Yu, R. W. Dutton, “Capacitance Reconstruction from Measured C-V in High Leakage Nitride/Oxide MOS,” IEEE Trans. Electron Devices, Vol. 47, NO. 10, pp. 1843-1850, Oct. 2000. [3.10] Y. C. Yeo, T. J. King, and C. Hu, “MOSFET Gate Leakage Modeling and Selection Guide for Alternative Gate Dielectrics Based on Leakage Considerations,” IEEE Trans. Electron Devices, Vol. 50, NO. 4, pp. 1027-1035, April 2003. [3.11] D. E. Ward and R. W. Dutton, “A Charge-Oriented Model for MOS Transistor Capacitance,” IEEE J. Solid-State Circuits, Vol. 13, NO. 5, pp. 703-708, Oct 1978. 第4章 [4.1] C. H. Choi, J. S. Goo, T. Y. Oh, Z. Yu, R. W. Dutton, A. Bayoumi, M. Cao, P. V. voorde, D. Vook, C. H. Diaz, “MOS C-V Characterization of Ultrathin Gate Oxide Thickness (1.3-1.8nm)”, IEEE Elec. Dev. Letters, Vol 20, NO. 6, pp. 292-294, June 1999. [4.2] C. H. Choi, Y. Wu, J. S. Goo, Z. Yu, R. W. Dutton, “Capacitance Reconstruction from Measured C-V in High Leakage Nitride/Oxide MOS,” IEEE Trans. Electron Devices, Vol. 47, NO. 10, pp. 1843-1850, Oct. 2000. [4.3] KWOK K. NG and RUICHEN LIU, “On the Calculation of Specific Contact Resistivity on <100> Si,” IEEE Trans. Electron Devices, Vol. 37, NO. 6, June 1990. [4.4] C. L. Hinkle, C. Fulton, R.J. Nemanich, and G. Lucovsky, ”Resonant tunneling in stacked dielectrics: a novel approach for obtaining the electron tunneling mass-conduction band offset energy products for advanced gate dielectrics,” Tokyo, IWGI 2003. [4.5] Y. C. Yeo, T. J. King, and C. Hu, “MOSFET Gate Leakage Modeling and Selection Guide for Alternative Gate Dielectrics Based on Leakage Considerations,” IEEE Trans. Electron Devices, Vol. 50, NO. 4, pp. 1027-1035, April 2003. [4.6] H.–S. P. Wong, “Beyond the conventional transistor,” IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002. 第5章 [5.1] Prashant Pandey, B. B. Pal, and S. Jit, “A New 2-D Model for the Potential Distribution and Threshold Voltage of Fully Depleted Short-Channel Si-SOI MESFETs,” IEEE Trans. Electron Devices, pp. 246-254, Feb. 2004. [5.2] N. R. Mohapatra, M. P. Desai, and V. R. Rao, “Detail Analysis of FIBL in MOS Transistor with High-K Gate Dielectrics,” IEEE Proceedings of the 16th International Conference on VLSI Design, 2003. [5.3] H.–S. P. Wong, “Beyond the conventional transistor,” IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002. [5.4] N. R. Mohapatra, A. Dutta, M. P. Desai, and V. R. Rao,” Effect of Fringing Capacitance in Sub 100nm MOSFET’s with High-K Gate Dielectrics,” VLSI Design, 14th International Conference on 3-7, pp. 479 – 482, Jan. 2001. [5.5] G. C. Y. Yeap, S. Kirishnan, and M. R. Lin, “Fringing-Induced Barrier Lowering(FIBL) in Sub-100nm MOSFETs with High-K Gate Dielectrics, “Electronics Letters, pp. 1150-1152, May 1998. [5.6] B. Cheng, M. Cao, R. Rao, A. Inani, P. V. Voorde, W. M. Greene, Johannes M. C. Stork, Z. Yu, Peter M. Zeitzoff, and Jason C. S. Woo, ”The Impact of High-k Gate Dielectrics and Metal Gate Electrodes on Sub-100 nm MOSFET’s, “ IEEE Trans. Electron Devices, pp. 1537-1544, July 1999. [5.7] B. Y. Tsui and L. F. Chin, “A Comprehensive Study on the FIBL of Nanoscale MOSFETs, “ IEEE Trans. Electron Devices, pp. 1733-1735, Oct. 2004. [5.8] S. C. Lin and J. B. Kuo, “Modeling the Fringing Electric Field Effect on the Threshold Voltage of FD SOI NMOS Devices with the LDD/Sidewall Oxide Spacer Structure, “IEEE Trans. Electron Devices, pp. 2559-2564, Dec. 2003. [5.9] S. C. Lin and J. B. Kuo, “Fringing-Induced Barrier Lowering (FIBL) Effects of 100nm FD SOI NMOS Devices with High Permittivity Gate Dielectrics and LDD/Sidewall Oxide Spacer, “ SOI Conf. Proc., pp.93-94, Oct. 2002. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/38837 | - |
dc.description.abstract | 本論文中提出了100奈米絕緣體上矽金氧半元件的本體和邊緣電容分析。
第二章說明不同氧化層厚度下,本體電容和邊緣電容彼此之間的關係。 第三章研究高介電係數材料作為閘極介電層時的本體電容及邊緣電容彼此的關係,以相同實際厚度或等效厚度為前提下,與傳統的氧化層作比較。 第四章探討閘極穿隧漏電流對元件電容特性的影響,以相同實際厚度或等效厚度為前提下,討論不同閘極介電層的穿隧現象。 第五章探討二維的元件物理特性,討論不同閘極介電層、邊牆材料、和汲極偏壓下,次臨界區域的邊緣引發位障下降現象。 | zh_TW |
dc.description.abstract | This thesis reports an analysis of intrinsic and fringing capacitance behavior in 100nm SOI (silicon on insulator) CMOS devices.
In chapter 2, we discuss the relationship between the intrinsic capacitance and the fringing capacitance with various oxide thicknesses. In chapter 3, we discuss the relationship between the intrinsic capacitance and the fringing capacitance with high-k gate dielectric. With the same physical thickness or effective thickness, we compare it with conventional oxide. In chapter 4, we discuss the tunneling effect on capacitance behavior. With the same physical thickness or effective thickness, we report the tunneling phenomenon with various gate dielectrics. Chapter 5 is related to 2D device physics, we discuss FIBL(fringing-induced barrier lowering) in subthreshold region with various gate dielectrics, sidewalls, and drain voltages. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T16:48:30Z (GMT). No. of bitstreams: 1 ntu-94-R92943120-1.pdf: 2163421 bytes, checksum: 6622a91866593d8a4aad9284c3fae341 (MD5) Previous issue date: 2005 | en |
dc.description.tableofcontents | 第1章 導論 1
1.1 SOI元件的簡介 1 1.2 SOI CMOS元件製程 4 1.3 氧化層材料的研究與發展 7 1.4 深次微米元件衍生的高電場及二維物理現象 8 1.5 本論文目標 10 第2章 邊緣電場效應對於不同閘極氧化層厚度的電容特性之影響 11 2.1 簡介 11 2.2 模擬結果 11 2.3 討論 16 2.3.1 U字型電場分佈 16 2.2.2 QC、QFD、QFS佔閘極總電荷之比例 17 2.4 結論 18 第3章 垂直及邊緣電通密度效應對於不同閘極介電層材料的電容行為之影響 19 3.1 簡介 19 3.2 模擬結果 20 3.2.1 不同閘極介電層材料的邊緣電容效應 20 3.2.2電容的兩階段上升現象 22 3.3 討論 25 3.3.1 Poly U字型及通道電場分佈 25 3.3.2 QC、QFD、QFS佔閘極總電荷之比例 27 3.3.3電子密度增量(∆nC)分佈與電容的關係 29 3.3.4 等效電容模型 31 3.4 結論 33 第4章 垂直及邊緣電通密度和穿隧漏電流效應對超薄元件電容行為之影響 35 4.1 簡介 35 4.2 模擬結果 37 4.2.1 模擬參數 37 4.2.2 電容行為 37 4.3 討論 39 4.4 結論 41 第5章 邊緣電場效應對於不同閘極介電層之次臨界區域之影響 42 5.1 簡介 42 5.2 模擬結果 43 5.2.1 汲極漏電流Ioff特性 43 5.2.2多晶矽閘極角落的轉角電場與DIBL 46 5.3 討論 47 5.3.1 VD=1V 47 5.3.2 VD=0.1V 49 5.4 結論 51 第6章 總結 52 參考文獻 54 第1章 54 第2章 55 第3章 55 第4章 57 第5章 58 | |
dc.language.iso | zh-TW | |
dc.title | 考慮高介電係數閘極介電層之100奈米絕緣體上矽金氧半元件之電容分析 | zh_TW |
dc.title | Analysis of Capacitance Behavior in 100 nm SOI CMOS VLSI Devices with High-K Gate Dielectrics | en |
dc.type | Thesis | |
dc.date.schoolyear | 93-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 蘇哿暐,林浩雄,王維新,賴飛羆 | |
dc.subject.keyword | 絕緣體上矽,高介電係數,電容, | zh_TW |
dc.subject.keyword | SOI,high k,capacitance, | en |
dc.relation.page | 59 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2005-06-27 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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