考慮閘極不對稱效應於雙閘絕緣體上矽金氧半元件，當上下閘極分別是N型和P型多晶矽閘極結構的分析

Abstract

本論文中提出考慮閘極不對稱效應於雙閘完全解離絕緣體上矽金氧半元件，當上下閘極分別是N+和P+多晶矽時的電容行為和臨界電壓模型的分析。 第一章主要是針對SOI元件做一個簡介，說明SOI元件與bulk元件比較之下有那些優點。 第二章則是探討通道長度為100奈米雙閘完全解離絕緣體上矽NMOS元件，當上下閘極分別是N+和P+多晶矽時，其獨特的電容現象。 第三章則是延續第二章的研究，但多考慮閘極不對稱效應，藉此來觀察元件內部的電容行為會發生什麼樣的改變。 第四章則是臨界電壓模型的推導和驗證，文中透過保角變換的技巧，簡化了不重疊區域內邊緣電場的分析，進而推導出更精確的臨界電壓模型，並藉由二維元件模擬軟體(MEDICI)驗證之。

This thesis reports an analysis of gate misalignment effect on capacitance behavior and threshold voltage of double-gate (DG) fully-depleted (FD) silicon on insulator (SOI) NMOS device with N+/P+ poly Top/Bottom gate. In chapter 1, we make an introduction for SOI device and describe its goods compared with the bulk one. In chapter 2, we discuss the unique capacitance phenomenon of a 100nm DG FD SOI NMOS device with the N+/P+ poly top/bottom gate. In chapter 3, we continue the research in chapter 2. Besides, we consider the gate misalignment effect on capacitance behavior and observe the change in it. In chapter 4, we describe the derivation and verification of threshold voltage of DG FD SOI NMOS device with N+/P+ poly Top/Bottom gate. By using the conformal mapping transformation approach, a model considering the fringing electric field effect in the non-gate overlap region of DG FD SOI NMOS device has been derived to provide an accurate prediction of threshold voltage behavior as verified by the 2D simulation results.