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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 胡振國(Jenn-Gwo Hwu) | |
dc.contributor.author | Chia-Wei Tung | en |
dc.contributor.author | 董佳衛 | zh_TW |
dc.date.accessioned | 2021-06-13T16:38:02Z | - |
dc.date.available | 2005-07-15 | |
dc.date.copyright | 2005-07-15 | |
dc.date.issued | 2005 | |
dc.date.submitted | 2005-07-05 | |
dc.identifier.citation | [1] International Technology Roadmap for Semiconductor, 2004 Update Semiconductor Industry Association.
[2] C. H Choi, Y. Wu, J. S. Goo, Z. Yu, and R. W. Dutton, “ Capacitance reconstruction from measured C-V in high leakage, nitride/oxide, MOS,” IEEE Trans. Electron Devices, vol.47, pp.1843-1850, 2000. [3] K. J. Yang and C. Hu, “ MOS capacitance measurements for high-leakage thin dielectrics,” ” IEEE Trans. on Electron Device, vol.46,no.7, July, 1999. [4] R. Rios et al, Tech. Dig. Int. Electron Devices Meet., pp.937-940,1995. [5] Berkeley Device Group. [Online]. Available: www.device.eecs.berkeley. edu/qmcv/html [6] T. O. Sedgewick, “Short Time Anneal,” J. Electrochem. Soc., vol.130, p.484, 1983. [7] J. C. Gelpey, P.O. Stump, and J.W. Smith, “Process Control for a Rapid Optical Annealing System,” Mat. Res. Soc. Symp. Proc., vol.52, p.199, 1986. [8] J. Nulman, “In-situ Processing of Silicon Dielectrics by Rapid Thermal Processing : Cleaning, Growth, and Annealing,” Mat. Res. Soc. Symp. Proc., vol.92, p.141, 1987. [9] J. H. Stathis, IBM J. Research & Development, 46(2-3), 265(2002). [10] B. E. Weir, M. A. A l a , P. J. Silverman, F. Baumann, D. Monroe, J. D. Bude, G. L. Timp, A. Hamad, Y. Ma, M.M. Brown, D. Hwang, T.W. Sorsch, A. Ghetti, G. D. Wilk. Solid-state Electronics, 46(3), 321(2002). [11] J. McPherson, V. Reddy, K. Banerjee, Le. Huy. Technical Digest, International Electron Devices Meeting 1998. p171. [12] G. Groesenken, R. Degraeve, B. Kaczer, H.E. Maes.Symposium on Structure and Electronic Properties of Ultrathin Dielectric Films on Silicon and Related Structures. (Materials Research Society Symposium Proceedings Vo1.592). p295, 2000. [13] C. Hu, Q. Lu. Proceedings, International Reliability Physics Symp. p47, 1999. [14] K. P. Cheung, Microelectronics Reliab., 41, 193, 2001. [15] Hector Sanchez, Belli Kuttanna, Tim Olson, Mike Alexander, Gian Georosa, Ross Philip, Joe Alvarez, “Thermal Management System for High Performance PowerPC Microprocessors,” in proceedings of Compcon ‘97 pp. 325-330, 1997. [16] E. H. Nicollian and J. R. Brew, “MOS (Metal Oxide Semiconductor) Physics and Technology,” John Wiley & Sons, 1982. [17] Mohamed Yehya Doghish and Fat Duen Ho, “A comprehensive Analytical Model for Metal-Insulator-Semiconductor (MIS) Devices,” IEEE Trans. Semiconductor. Manufact., vol. 39, No. 12, p.2771, 1992. [18] Kevin J. Yang and Cheming Hu, “MOS capacitance Measurements for High-Leakage Thin Dielectric,” IEEE Trans. Electron Devices, pp.1500, 1999. [19] Kevin Yang, Ya-Chin King, and Cheming Hu, “Quantum Effect in Oxide Thickness Determination From Capacitance Measurement,” 1999 Symposium on VLSI Technology, Digest of Technical Paper, pp. 77, 1999. [20] Z. H. Chen, S. W. Huang, J. G. Hwu, “Electrical characteristics of ultra-thin gate oxides ( less than or equal 3 nm) prepared by direct current superimposed with alternating-current anodization” Solid-State Electronics, v 48, n 1, p 23-28, 2004. [21] B. J. Mrstik, V. V. Afanas'ev, A. Stesmans, and P. J. McMarr, “Relationship between hole trapping and oxide density in thermally grown SiO2” Microelectronic Engineering, v 48, n 1-4, p 143-146, 1999. [22] D. M. K. Quazi, N. Yasuda, K. Taniguchi, and C. Hamaguchi, “Hole trapping and detrapping characteristics investigated by substrate hot-hole injection into oxide of metal-oxide-semiconductor structure” Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes & Review Papers, v 33, n 1B, p 668-671, 1994. [23] Tomasz Brozek, Eric B. Lum, and Chand R. Viswanathan, 'Oxide thickness dependence of hole trap generation in MOS structures under high-field electron injection' Microelectronic Engineering, v 36, n 1-4, p 161-164, 1997. [24] D. J. DiMaria, 'Hole trapping, substrate currents, and breakdown in thin silicon dioxide films' IEEE Electron Device Letters, v 16, n 5, May, 1995, p 184-18D. J. DiMaria, R. Ghez, and D. W. Dong, “Charge trapping studies in Si02 using high current injection from Si-rich Si02 films,” J. Appl. Phys., vol. 51, no. 9, pp. 4830-4841, 1980. [25] P. P. Apte and K. C. Saraswat, “Correlation of trap generation to chargeto-breakdown ( Q b d ) : A physical damage model of dielectric breakdown,” ZEEE Trans. Electron Devices, vol. 41, no. 9, pp. 1595-1601, 1994. [26] C. H. Bjorman, J. T. Fitch, and G. Lucovsky, Appl. Phys. Lett., 56,p 1983, 1990. [27] A. Hamada, T. Fursawa, N. Saito, and E. Takeda, IEEE Trans. Electron Devices, 38, 895, 1991. [28] H. Miura, S. Ikeda, and Suzuki, Tech. Dig. Int. Electron Devices Meet.,743, 1996. [29] J. M. Kim, Y. K. Kim, 'The saw-damage-induced structural defects on the surface of silicon crystals' Electrochemical Society Proceedings, v 5, High Purity Silicon VIII - Proceedings of the International Symposium, p 27-35, 2004. [30] C. Paydenkar, A. Poddar, H. Chandra, and S. Harada, 'Wafer sawing process characterization for thin die (75 micron) applications' Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium, v 29, IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium, p 74-77, 2004. [31] S. W. Huang, and J. G.. Hwu 'Electrical Characterization and Process Control of Cost-Effective High-k Aluminum Oxide Gate Dielectrics Prepared by Anodization Followed by Furnace Annealing' IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 7, JULY 2003. [32] K.P. Cheung, 'Temperature effect on ultra thin SiO/sub 2/ time-dependent-dielectric-breakdown' Plasma- and Process-Induced Damage, 2003 8th International Symposium 24-25 ,Page(s):134 – 137, 2003. [33] J. W. McPherson, D. A. Baglee. Proceedings, Intemation Reliability Physics Symposium (IRPS). 1985. pl. [34] Z. A. Weinberg, Appl. Phys. Lett., 27(8), 437( 1975). [35] Z. A. Weinberg, D. R. Young, D.J. DiMaria, G.W. Rubloff, J. Appl. Phys., 50(9), 5757(1979). [36] D. J. DiMaria, J. W. Stasiak, J. Appl. Phys. 65(6), 2342( 1989). [37] D. A. Buchanan and D. J. DiMaria, J. Appl. Phys. 67, 7439 (1990). [38] D. R. Young, A. E. Irene, D. J. DiMaria, R. F. DeKeersmaecker, and H. Z. Massoud, J. Appl. Phys. 50, 6366 (1979). [39] F. J. Feigl, D. R. Young, D. J. DiMaria, S. K. Lai, and J. Calise, J. Appl. Phys. 52, 5665 (1981). [40] D. J. DiMaria, Appl. Phys. Lett. 51, 655 (1987). [41] C. T. Sah, J. Y. C. Sun, and J. J. Tsou, J. Appl. Phys. 54, 5864 (1983). [42] C. T. Sah, J. Y. C. Sun, and J. J. Tsou, J. Appl. Phys. 55, 1525 (1984). [43] R. Gale, F. I. Feigl, C. W. Magee, and D. R. Young, J. Appl. Phys. 54, 6938 (1983). [44] N. S. Saks, 11. B. Klein, and D. L. Griscom, IEEE Trans. Nucl. Sci. NS-35, 1234 (1988). [45] N. S. Saks and D. B. Brown, IEEE Trans. Nucl. Sci. NS-36, 1848 (1989). [46] See a review in D. L. Griscom, The Physics of SiO, and Its Interfaces, edited by S. T. Pantelides (Pergamon, New York, 1978), p. 232; D. L. Gtiscom, D. B. Brown, and N. S. Saks, The Physics and Chemfstry of 30, and the Si-Si02 Interface, edited by C. R. Helms and B. E. Deal (Plenum, New York, 1988), p. 287. [47] R. E. Stahlbush, B. J. Mrstik, and R. K. Lawrence, IEEE Trans. Nucl. Sci. NS-37, 1641 (1990). [48] L. DoThanh and P. Balk, J. Electrochem. Sot. 135, 1797 (1988). [49] M. L. Reed and J. D. Plummer, .Appl. Phys. Lett. 51, 5 14 (1987). [50] D. Vuillaume, D. Goguenheim, and J. C. Bourgoin, Appl. Phys. Lett. 58, 490 (1991) [51] M. V. Fischetti and B. Ricco, J. Appl. Phys. 57, 2854 (1985). [52] M. V. Fischetti, J. Appl. Phys. 56, -577 (1984). [53] T. Sakurai and T. Sueano. J. ADDS. Phvs. 52, 2889 (1981). [54] F. J. Grunthaner, B. F. Lewis, N. Zamini, J: Maser&n, and A. Madhukar, IEEE Trans. Nucl. Sci. NS-27, 1640 (1980). | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/38579 | - |
dc.description.abstract | 在互補式金氧半導體製程技術上,基礎是建立在金氧半結構,自從金氧半導體場效電晶體發明以來,二氧化矽已經被用以作為其閘極氧化層超過四十年,因為二氧化矽擁有極佳的穩定性與均勻度並且製程簡單。當元件的尺寸為了獲得更佳的密度和性能而縮小時,氧化層的厚度也隨之縮小;然而,隨著製程技術的縮小亦造成更大的功率消耗與封裝密度,因此產生兩個問題需要被考慮,其中一個問題為高溫熱效應在元件性能上的影響,另一個問題為晶圓切割所造成的影響。在互補式金氧半導體製程技術中,應力相關的問題已經成為重要的課題,為數不少的元件由於操作在高溫狀態及在晶圓切割效應下,因而衰退故障。在本篇論文中,我們將致力於應力問題上的研究,用以判斷在熱效應上的改善度;藉由分析金氧半電容結構的電特性來研究矽基板與二氧化矽氧化層系統的應力效應。
在第二章,為了研究熱效應所造成的影響,我們將金氧半電容元件放置於100oC的烤箱內三十秒持續數次,並額外施以不同的外加應力(壓縮及拉伸基板)來觀察其變化;藉由量測電流變化程度和定電壓應力來比較其電特性,實驗結果發現拉伸溫度施壓(tensile-temperature stress)呈現出最好的特性。 此外,在第三章,考慮晶圓切割的影響,我們把晶圓切成條狀並重複之前的實驗程序;我們發現切割確實在金氧半電容元件上造成極大的影響,電流變化程度遠大於未切割之元件;另外,我們觀察到切割過後的元件在經過預先的電性量測,會造成在電流在P型基板的累積區上升,此現象是於未經切割的元件所觀察不到的。 | zh_TW |
dc.description.abstract | The metal-oxide-semiconductor (MOS) structure is the groundwork of complementary metal-oxide-semiconductor (CMOS) technology. Silicon oxide has been used as a gate dielectric of MOSFETs for more than forty years since MOSFET had been introduced due to its excellent stability, uniformity, and easy fabrication process. As the size of device scales down for higher density and performance, the thickness of silicon oxide also scales down. However, as technology downscaling causes greater power and package densities, two issues should be considered. One is the thermal effect on device performance and the other is the influence of wafer-sawing. The stress-related problems have become important issues in the CMOS technology. Many device failures are caused by the stresses at occur during high temperature operations and wafer-sawing. In this thesis we will focus on the study of mechanical stress problems to verify the improvement of thermal effect. We will analyze the electrical characteristics of the MOS structure to study the stress effect on Si/SiO2 system.
In chapter 2, we investigated the thermal effect for MOS capacitors after receiving consecutive thermal treatments at 100oC for 30 seconds with various mechanical stresses applied on the substrate. And the measurements of current variation and constant voltage stress (CVS) were made to compare their electrical characteristics. The experimental result shows tensile-temperature stress exhibits the best properties. Furthermore, in chapter 3, for wafer-sawing consideration, we scribed the wafer into the form of a strip and repeated the processes above. We found that scribing result in significant influence on MOS capacitor. The current variations are larger than those without scribing. In addition, we observed that electrical pre-measurement will cause the current level to increase in accumulation region. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T16:38:02Z (GMT). No. of bitstreams: 1 ntu-94-R92943130-1.pdf: 1032221 bytes, checksum: a353cd54886ffbb16aaac12d07d5adde (MD5) Previous issue date: 2005 | en |
dc.description.tableofcontents | Chapter 1 Introduction 1
1-1 Motivation of This Work 1 1-2 Equivalent Oxide Thickness (EOT) 2 1-3 Rapid Thermal Processing System 4 1-4 Measurement System 5 Chapter 2 Characteristics of MOS(P) Device under Strain- Temperature Stressing in the form of a Full Wafer 10 2-1 Introduction 10 Saturation gate current for strong inversion MOS capacitor 11 2-2 Experimental 13 2-3 Results and Discussion 14 2-3-1 Changes in Current-Voltage (I-V) Behavior 15 2-3-2 Investigation of Trapping Behavior during Constant Voltage Stress (CVS) 17 2-4 Summary 18 Chapter 3 Characteristics of MOS(P) Device under Strain- Temperature Stressing in the form of a Strip 32 3-1 Introduction 32 Classical Theory of Gate Capacitances in MOS Devices 33 3-2 Experimental 34 3-3 Results and Discussion 35 3-3-1 Changes in Current-Voltage (I-V) behavior 35 3-3-2 Changes in Capacitance-Voltage (C-V) behavior 36 3-3-3 Influence on Electrical Measurement 37 3-3-4 Kinetic Model 38 3-4 Summary 40 Chapter 4 Conclusion and Suggestions for Future Work 56 4-1 Conclusion 56 4-2 Suggestions for Future Work 57 References 59 | |
dc.language.iso | en | |
dc.title | 超薄閘極氧化層形變溫度施壓效應之研究 | zh_TW |
dc.title | Investigation of Strain-Temperature Stress on Rapid Thermal Ultra-thin Gate Oxides | en |
dc.type | Thesis | |
dc.date.schoolyear | 93-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 鄭晃忠(Huang-Chung Cheng),洪志旺(J.W. Hong) | |
dc.subject.keyword | 金氧半電容,二氧化矽,熱效應,晶圓切割,應力效應,形變, | zh_TW |
dc.subject.keyword | MOS,capacitor,oxide,strain,temperature,tensile,compressive,CVS,breakdown,variation, | en |
dc.relation.page | 64 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2005-07-06 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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