5-bit 10Gb/s 追蹤與保持電路的設計與實作

Abstract

在深次微米的互補式金氧半導體電路中，在類比數位轉換器的實現上，高速的追蹤保持電路是一個基本且不可或缺的元件，追蹤保持電路的架構可分為兩大類，一是閉迴路的架構，另一類則是開迴路的架構。閉迴路架構的追蹤保持電路擁有高解析度的特性，但是，其取樣速度卻無法達到太快，開迴路架構的追蹤保持電路則是相反，擁有較高速的取樣速度，但卻無法擁有較高的解析度。這兩種電路在目前只能視用途目的而使用不同的架構，並無法有同時擁有兩者兼顧的優點。 在此論文研究當中，一個五位元每秒一百億次的追蹤保持電路在0.18微米互補式金氧半導體製程已經被設計出來。我們提出了一種以開迴路架構為原則的電路，利用電晶體高頻特性，將因為高頻效應所導致的非線性現象降低，加以提升在高速操作下的解析度。

In CMOS circuits, a high-speed track-and-hold circuit is a fundamental and indispensable component in an A/D converter. The track-and-hold amplifier can be classified as the open-loop and the closed-loop architectures. The closed-loop architecture has the characteristic of higher resolution and lower speed. On the contrary, the open-loop architecture has the characteristic of lower resolution and higher speed. Consequently, different kinds of track-and-hold circuits will be needed based on the purpose of the applications. Now no architecture can have both the advantages at the same time. In this thesis, a 5-bit 10Gb/s track-and-hold circuit has been designed and implemented in a standard 0.18-um CMOS process. It utilizes the high frequency characteristic of MOS transistors to reduce the nonlinearity due to the effect of high-frequency and raise the resolution under high-frequency operation.