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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/38219完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳少傑 | |
| dc.contributor.author | Chia-Ching Lin | en |
| dc.contributor.author | 林家慶 | zh_TW |
| dc.date.accessioned | 2021-06-13T16:28:11Z | - |
| dc.date.available | 2009-07-27 | |
| dc.date.copyright | 2005-07-27 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-07-14 | |
| dc.identifier.citation | [1] K. Pahlavan, A. Zahedi and P. Krishamurthy, “ Wideband local access Wireless LAN and wireless ATM,” IEEE Communication Magzane.,pp34-40,NOV 1997.
[2] S.-O. Lee, M. Yoh, J. Lee, and I. Ryu, “A 17mW, 2.5Ghz fractional-N frequency synthesizer for CDMA2000,” in Proc. ESSCIRC’01, 2001. [3] B. Razavi, RF Microelectronics, Pretice-Hall, Inc., 1998. [4] M.H. Perrott, T.L. Tewksbury,and C.G. Sodini, “A 27mW CMOS fractional-N synthesizer using digital compensation for 2.5Mb/s GFSK modulation,” IEEE JSSC, vol.32, pp.2048-2060,Dec,1997. [5] J. Craninckx and M. Steyaert,” A 1.75GHz/3V dual modulus divide-by 128/129 prescaler in 0.7um CMOS,” IEEE JSSC, vol.31, pp.890-897, Jul., 1996. [6] N. Filiol et al., “An agile ISM band frequency synthesizer with built-in GMSK modulation,’ IEEE JSSC, vol.33, pp.998-1008, Jul., 1998. [7] T.A. Riley and M.A. Copeland, ”A simplified continuous phase modulator,” IEEE Trans. Circuit and Systems,vol.41,pp.321-328,May,1994. [8] W.T. Bax and M.A. Copeland,” A GSM modulator using a delta sigma frequency discriminator based synthesizer,” ISCAS, pp.498-501, 1998. [9] S.O. Lee et al.,” A 17mW, 2.5GHz fractional-N frequency synthesizer for CDMA-2000,” ESSCIRC, Sep., 2001. [10] D. Theil et al., “A fully Integrated CMOS frequency synthesizer for Bluetooth,'IEEE RFIC Symposium, pp.103-106, 2001. [11] Behzad Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall,1998. [12] F.M. Gardner, “Charge-Pump Phase-Lock Loops,“ IEEE Trans. on Communications, vol. 28, pp. 1849-1858, Nov. 1980. [13] W.O. Keese, “An analysis and performance evaluation of a passive filter design technique for charge pump phase-locked loops,” National Semiconductor Application Note, no. 1001, May 1996. [14] 郭俊儀, “ Design of a Low Noise Frequency Synthesizer for 802.11a,” Master Thesis, NTU GIEE 2004. [15] Shenggao Li, “High performance GHz RF CMOS ICs for Integrated phase-locked loops” Ph. D Dissertation, The Ohio State University,2000. [16] D.A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley and Sons, Inc., 1997. [17] W. Rhee, B.S. Song and A. Ali, ”A 1.1GHz CMOS fractional-N frequency synthesizer with a 3-bit third-order SD odulator”,JSSC,vol.35,pp.1453-1460, Oct., 2000. [18] J. Craninckx and M. Steyaert, ”Low Noise Voltage-controlled oscillators using enhanced LC-tank,” ISCAS, vol.42, pp794-804, Dec. 1995. [19] Emad Hegazi, Asad A.Abidi, ”A Filtering Technique to Lower LC Oscillator Phase Noise,” JSSC vol36, Dec. 2001. [20] T.A.Riley, M.Copeland and T.Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE JSSC, vol.28, pp.553-559, Mar.1996. [21] T.Kenny et al., ”Design and realization of a digital SD modulation for fractional-n frequency synthesis,” IEEE Trans.Vehicular Technlogy, pp.510-521.Mar,1999. [22] B De Muer, M.Steyaert, ” A CMOS monolithic SD-controlled fractional-N frequency synthesizer for DCS-1800,” IEEE JSSC, vol.37, pp835-844, Jul. 2002. [23] M.Kozak and I. Kale,”A pipelined noise shaping coder for fractional-N frequency synthesis,” IEEE Trans Instrumentation and Measurement, pp1154-1160, Oct 2001. [24] Keshab K,Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. New York: John Wiely&Sons, Inc.,1999. [25] 邱繼崑, “Design and Realization of CMOS RF Frequency Synthesizer,” Master Thesis, NTU GIEE 2001. [26] 陳威良, “A 5.8-GHz Delta-Sigma Fractional-N Frequency Synthesizer,”Master Thesis, Yuan Ze University 2003. [27] 楊清淵, “Design of Clock Synchronizers and Frequency Synthesizers,” Master Thesis, NTU GIEE 2000 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/38219 | - |
| dc.description.abstract | 在今日的射頻前級電路中，本地震盪器是一個不可或缺的要件，而設計一個兼具快速的鎖定速度、低相低雜訊和高頻率解析度的頻率合成器也成為一個挑戰。本論文探討MASH的三角積分調變器對於頻率合成器輸出相位雜訊的影響，另外由積體電路實現一個整合性的除小數頻率合成器，並使用MASH 1-1-1 三角積分調變器作為除頻數之調變，一方面藉由打亂除頻器的模數得到較好雜訊抑制，另一方面將雜訊推至較高頻的頻率，而能被鎖相迴路所澸除。此頻率合成器使用0.18μm Mixed-signal 1P6M CMOS製程，可操作於4GHz，模擬的相位雜訊在1MHz處為-115dBc/Hz，並在600MHz的跳頻間距下可達到小於30μm的鎖定時間。 | zh_TW |
| dc.description.abstract | Nowadays, local oscillator is an essential component of the RF front-end. And the design for a frequency synthesizer with agile settling speed, low phase noise and high frequency resolution has become a challenge. The thesis discusses the influence of the MASH Sigma-Delta Modulator (SDM) to the synthesizer output phase noise. The integrated fractional-N frequency synthesizer is implemented with MASH 1-1-1 SDM. On one hand, better fractional and reference spurious suppression is achieved by randomizing the modulus of frequency dividers; on the other hand, the spurious noise is push to higher frequency and will be further filtered out by the PLL. The frequency synthesizer is operated over 4GHz. The simulated phase noise is -115dBc/Hz at 1MHz offset, and the settling time is less than 30μs at 600MHz frequency jumping. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T16:28:11Z (GMT). No. of bitstreams: 1 ntu-94-R92943085-1.pdf: 1586806 bytes, checksum: 5bd8c9416c0564845985d21794737ea3 (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | ABSTRACT…………………………………………………………………v
LIST OF FIGURE……………………………………………………… xi LIST OF TABLES……………………………………………………… xv CHAPTER 1 INTRODUCTION………………………………………………1 1.1 Motivatio………………………………………………………… 1 1.2 Various Types of Frequency Synthesizer Architectures…2 1.2.1 Digital Synthesizer………………………………………… 2 1.2.2 Direct Synthesizer……………………………………………3 1.2.3 PLL-Based Synthesizer……………………………………… 3 1.2.4 Fractional-N Synthesizer……………………………………5 1.3 Fractional-N Synthesis in Various CommunicationSystems8 1.4 Thesis Organization…………………………………………… 9 CHAPTER 2 THE BASICS OF FREQUENCY SYNTHESIZER………………11 2.1 General Considerations……………………………………… 11 2.1.1 Phase Noise……………………………………………………12 2.1.2 Spurs……………………………………………………………13 2.2 Phase Locked Loop(PLL) Fundamentals………………………14 2.2.1 Voltage Controlled Oscillator(VCO)…………………… 15 2.2.2 Phase Frequency Detector(PFD)……………………………16 2.2.3 Charge Pump(CP)………………………………………………19 2.2.4 Loop Filter……………………………………………………21 2.3 Phase Noise Performance Analysis………………………… 23 2.3.1 Noise at Input……………………………………………… 23 2.3.2 Noise of VCO………………………………………………… 25 2.4 Charge-Pump PLL Design……………………………………… 26 2.4.1 Second-Order PLL…………………………………………… 26 2.4.2 Third-Order PLL………………………………………………29 2.4.3 Fourth-Order PLL…………………………………………… 32 CHAPTER 3 SYBTHESIZER ARCHITECTURE BEHAVIORAL SIMULATION 35 3.1 Design Specification………………………………………… 35 3.2 Synthesizer Architecture…………………………………… 36 3.3 Behavioral Simulation…………………………………………36 3.3.1 Integer-N PLL Model…………………………………………38 3.3.2 Dual-Controlled Integer-N PLL Model……………………40 3.3.3 Fractional-N PLL Model…………………………………… 42 CHAPTER 4 DESIGN OF FREQUENCY SYNTHESIZER……………………47 4.1 PLL Building Blocks……………………………………………47 4.1.1 Phase Frequency Detector(PFD)……………………………47 4.1.2 Charge Pump(CP)………………………………………………49 4.1.3 Loop Filter(LF)………………………………………………50 4.1.4 Voltage Controlled Oscillator(VCO)…………………… 53 4.1.5 Multi-Modulus Divider(MMD)……………………………… 55 4.2 Sigma-Delta Modulator…………………………………………57 4.2.1 Modulator Topology………………………………………… 58 4.2.2 Implementation of Pipelined MASH 1-1-1 Modulator… 60 CHAPTER 5 SIMULATION AND MEASUREMENT RESULTS……………… 65 5.1 Mixed Signal Design Flow…………………………………… 65 5.2 Simulation Tools……………………………………………… 67 5.3 Simulation Results…………………………………………… 67 5.3.1 Simulation Results of PFD and Charge Pump……………68 5.3.2 Simulation Results of VCO…………………………………71 5.3.3 Simulation Results of MMD…………………………………73 5.3.4 Simulation Results of MASH 1-1-1 SDM………………… 74 5.3.5 Closed-Loop Simulation ……………………………………76 Reference………………………………………………………………80 | |
| dc.language.iso | en | |
| dc.subject | 三角積分調變 | zh_TW |
| dc.subject | 頻率合成器 | zh_TW |
| dc.subject | fractional-n | en |
| dc.subject | delta-sigma modulate | en |
| dc.subject | frequency synthesizer | en |
| dc.title | 三角積分調變除小數頻率合成器之設計及實作 | zh_TW |
| dc.title | Design and Implementation of a Sigma-Delta
Modulated Fractional-N Frequency Synthesizer | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵,林宗賢,李泰成 | |
| dc.subject.keyword | 頻率合成器,三角積分調變, | zh_TW |
| dc.subject.keyword | frequency synthesizer,delta-sigma modulate,fractional-n, | en |
| dc.relation.page | 82 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2005-07-14 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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