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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃天偉 | |
| dc.contributor.author | Yi-Chun Huang | en |
| dc.contributor.author | 黃益群 | zh_TW |
| dc.date.accessioned | 2021-06-13T16:26:47Z | - |
| dc.date.available | 2008-07-22 | |
| dc.date.copyright | 2005-07-22 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-07-14 | |
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[14] Kyutae Lim, Stephane Pinel, Mekita Davis, Albert Sutono, Chang-Ho Lee, Deukhyoun Heo, Ade Obatoynbo, Joy Laskar, Emmanouil M. Tantzeris, Rao Tummala, “RF-System-On-Package (SOP) for Wireless Communications, ” IEEE Microwave Magazine, Vol. 3, pp. 88-99, Mar. 2002. [15] D. Bhattacharya; A. Grochowski; K. Laker; T.R. Viswanathan, “Integrated circuit testing for quality assurance in manufacturing: history, current status, and future trends,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 44, pp. 610-633, Aug 1997. [16] A. Kafton, “Wireless SoC testing: can RF testing costs be reduced?” 2002 International Test Conference Proceedings, pp. 1226 -1226. 2002. [17] Glajchen, Deon, “RF instrument accuracy - Some effects of measurement uncertainty,” 1993 Fifteenth IEEE/CHMT International Electronic Manufacturing Technology Symposium Proceedings, pp. 19-21. Oct 1993. [18] A. Chatterjee; S. Cherubal; R. Voorakaranam, “A signature test framework for rapid production testing of RF circuits,” 2002 Design, Automation and Test in Europe Conference and Exhibition Proceedings, pp. 186-191. 2002. [19] E. Strid, “Roadmapping RFIC test,” 1998 GaAs IC Symposium Technical Digest, pp. 3-6. 1998. [20] Lee Meyer, Peter Cain, “Bluetooth Measurements - RF Tests Overview,” Wireless Symposium Conference Presentation, Feb. 2001. [21] G. D. Gregorio, M. G. L. Rosa, and B. Russo “Checkers for RF Matching Networks on an Automatic Test Board,” IEEE International on-line Testing Workshop, pp.170-173, 2002. [22] J. Dabrowski, J.G. Bayon, “Loopback BiST for RF Front-Ends in Digital Transceivers,” IEEE Defect and Fault Tolerance in VLSI Systems, pp.220-228, 2004. [23] A. Halder, S. Bhattacharya, G. Srinivasan, A. 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[29] T. Das, A. Gopalan, C. Washburn, and P.R. Mukund, “Dynamic Input match correction in RF Low Noise Amplifiers, Proc. Of 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.211-219, 2004. [30] R. J. Russell, “Boundary scan architecture analog extension,” U.S. Patent, patent number:5,404,358, 1995. [31] Sedra, A. S. , and K.C. Smith, “Microelectronic Circuits 4th edition,” 1997. [32] T. Wiemers, and J. V. D. Boom, “Circuit configuration for preparing analog signals for a boundary scan test process,” U.S. Patent, patent number:5,563,523, 1996. [33] M. Gion, and M. Hirose, “Analog boundary scan compliant integrated circuit system,” U.S. Patent, Patent number: 6,681,355 B1. [34] R.C. Liu, C.R. Lee, H. Wang, and C.K. Wang, “A 5.8-GHz two-stage high-linearity low-voltage low noise amplifier in a 0.35 CMOS technology,” IEEE RFIC Symposium, pp.221-224, June 2002. [35] T. W. Huang, P. S. Wu, R. C. Liu, and J. H. Tsai, H. Wang, T.D. Chiueh, “Boundary scan for 5-GHz RF pins using LC isolation networks,” IEEE VLSI Test Symposium,pp.347-350, April 2004. [36] T.W. Huang, Y. C. Huang, J. H. Tsai, P.S. Wu, “Miniature broadband Isolation Networks for GHz RF Boundary Scan Test,” VLSI Symposium, Taiwan, Aug. 2004 [37] M. Soma, “Fault Coverage of DC Parametric Tests for Embedded Analog Amplifiers,” IEEE International Test Conference, pp. 566-573, Oct. 1993. [38] EDN Magazine, www.ednmag.com [39] SMT Magazine, www.smtmag.com [40] J.-L. Carbonero, “Bringing Wireless Test to the Mainstream, ” Presented in Innovative Practice Session- Latest Results in Wireless Test,” in VLSI Test Symposium, 6C.2, April 2004. [41] Winspring Technology WS9001 data sheet. [42] Win 2 HBT model handbook. [43] S. Cripps, “RF Power Amplifier for wireless communications,” Artech House, 1999. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/38130 | - |
| dc.description.abstract | 當大量生產射頻積體電路時，由於昂貴的測試儀器及許多需要細心的測試步驟，使得測試成本佔生產成本相當大的比例。射頻電路的測試並不像成熟度極高的數位電路測試，它依然是一個嶄新的領域，值得投入更多的研究。而到目前所提出的測試方法有非常多，但這些方法大多缺乏應用的普遍性。
本論文的第一部份是利用週邊掃瞄電路與射頻電路的結合。週邊掃瞄電路是國際電子電機協會中的一個測試標準，並廣泛地在數位電路中使用。因此我們提出利用此現有的標準將其應用於射頻電路中作為新的應用，我們必須採用電感電容以及電阻電容的隔離電路，來連接週邊掃瞄電路與射頻電路。經由比較過後我們發現電阻電容的隔離電路比起電感電容的隔離電路有更寬的隔離度頻寬與更小的晶片面積。 第二個部分是射頻放大器的錯誤涵蓋率分析，包括了低雜訊放大器與功率放大器。我們發現錯誤涵蓋率會呈現一個U狀的分佈，也就是說明測試方法有其測試的極限。此外我們也作了良率的分析，最後發現良率與錯誤涵蓋率有著互補的關係。此外，所給定的規格也是影響錯誤涵蓋率與良率的重要因素之一。有了以上的概念後，只需採用適當的設計概念加上簡單的測試方法，就可以快速檢測在大量生產時的射頻放大器。 | zh_TW |
| dc.description.abstract | Test cost is one of the key contributors to fabricate radio frequency integrated circuits (RFICs) due to the relatively expensive equipments cost and the tedious tests procedure. RF test, unlike digital test which has developed for more than three decades, is still a new research domain left more investigations. Some researches are presented in various papers are loss of generality.
The first part of this thesis is related to using boundary scan cell as the RFIC structural test circuits. Boundary scan, which is IEEE 1149.1 standard, is adopted in digital circuits universally. We use this available resource and apply it to the RF circuits as a new application. The isolation networks to combine the RF circuits and boundary scan cell are by LC or RC circuits. RC isolation networks achieve broader isolation bandwidth and smaller size than LC ones. The second part is the fault coverage analysis of RF amplifiers, both LNA and PA. We find fault coverage has the U-shaped window, which presents the finite ability to detect faults. Besides, we also perform yield analysis. We consider the yield is the complementary effect to the fault coverage. Moreover, specifications are also the dominating factor to affect fault coverage and yield. Having these concepts, it is possible to design RF amplifiers and test them in simple methods. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T16:26:47Z (GMT). No. of bitstreams: 1 ntu-94-R92942016-1.pdf: 2889402 bytes, checksum: 18e6bc88614905c3c124dfd5834ec7df (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | Chapter 1 Introductions
1.1 Background........................................1 1.2 Motivations.......................................3 1.3 Test Issues in Digital and Analog Circuits........4 1.4 Test Cost in RF Circuits..........................7 1.5 Contributions....................................11 1.6 Organizations....................................12 Chapter 2 Fundamentals and Current Research 2.1 RF Fundamentals..................................13 2.2 Test Fundamentals................................21 2.3 Paper discussions................................31 2.3.1 Components Checkers........................31 2.3.2 Loop back Approach.........................34 2.3.3 Signature Test Approach....................37 2.3.4 Time Domain Measurement....................40 2.3.5 Built-in Self-test (BIST)..................43 2.4 Summary..........................................44 Chapter 3 GHz RF Boundary Scan 3.1 Structural test..................................47 3.2 Boundary Scan....................................49 3.3 American Analog BSC Patent.......................51 3.4 RF BSC with Isolation Network....................54 3.4.1 LNA........................................54 3.4.2 LC Isolation Networks......................55 3.4.3 RC Isolation Networks......................60 3.4.4 RC and LC Isolation Circuits Comparison....63 3.5 Summary of RF BSC and Analog BSC.................65 Chapter 4 Analysis Parametric Fault Coverage for GHz Amplifiers 4.1 Basic Idea.......................................67 4.2 Fault Modeling and its Considerations............69 4.3 LNA Analysis.....................................71 4.4 PA Circuits Analysis.............................80 4.5 PA Analysis......................................89 4.6 Fault Coverage and Yield Analysis................96 4.7 Specifications, Yield and Fault Coverage........104 4.8 Summary.........................................106 4.9 Suggestive Test Flow Chart......................107 Chapter 5 Conclusion..........................................108 Reference...........................................111 | |
| dc.language.iso | en | |
| dc.subject | 射頻電路測試 | zh_TW |
| dc.subject | 射頻電路 | zh_TW |
| dc.subject | 射頻放大器 | zh_TW |
| dc.subject | RF amplifiers | en |
| dc.subject | RF circuits | en |
| dc.title | 具高度可測試性之射頻放大器分析 | zh_TW |
| dc.title | The Analysis of High Testability RF Amplifiers | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 王暉,洪子聖,陳怡然,廖信行 | |
| dc.subject.keyword | 射頻電路,射頻電路測試,射頻放大器, | zh_TW |
| dc.subject.keyword | RF circuits,RF amplifiers, | en |
| dc.relation.page | 115 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2005-07-15 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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