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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 林茂昭 | |
dc.contributor.author | Ming-Che Lu | en |
dc.contributor.author | 呂明哲 | zh_TW |
dc.date.accessioned | 2021-06-13T16:26:19Z | - |
dc.date.available | 2007-07-20 | |
dc.date.copyright | 2005-07-20 | |
dc.date.issued | 2005 | |
dc.date.submitted | 2005-07-15 | |
dc.identifier.citation | [1] R. Gallager, ”Low-density parity-check codes”, Cambridge, MA: MIT Press, 1963.
[2] R. M. Tanner, ”A recursive approah to low complexity codes”, IEEE Tans. Information Theory, pp. 533-547, Sept. 1981. [3] M. Luby, M. Mitzenmacher, A. Shokrollahi, and D. Spielman, ”Analysis of low density codes and improved designs using irregular graphs”, in Proc. 30th Annu. ACM Symp. Theory of Computing, 1998, pp.249-258. [4] T. J. Richardson, A. Shokrollahi, and R. Urbamke, ”Efficient encoding of low-density parity-check codes”, IEEE Trans. Inform. Theory, vol. 47, pp.638-656, Feb. 2001. [5] T. J. Richardson and R. Urbamke, ”The capacity of low-density parity check codes under message-passing decoding”, IEEE Trans. Inform. Theory, vol. 47, pp.599-618, Feb. 2001. [6] D. J. C . Mackay, ”Good error-correcting codes based on very sparse matrices”, IEEE Trans. Inform. Theory, vol. 42, pp.1710-1722, Nov. 1996. [7] http://www.inference.phy.cam.ac.uk/mackay/codes/data.html [8] Y. Kou, S. Lin, and Marc P. C. Fossorier, ”Low-density parity-check codes based on finite geometries: a rediscovery and new results”, IEEE Trans. Inform. Theory, vol. 47, pp.2711-2736, Nov. 2001. [9] S. Lin and D. J. Costello, Jr., ”Error control coding: fundamentals and applications”, Prentice Hall, Englewood Cliffs, New Jersey, 1983. [10] T. J. Richardson, A. Shokrollahi, and R. Urbamke, ”Design of capacity-approaching irregular low-density parity check codes”, IEEE Trans. Inform. Theory, vol. 47, pp.619- 637, Feb. 2001. [11] J. Xu, L.Chen, I. Djurdjevic, S. Lin, and K. Abdel -Ghaffar, ”Construction of Regular and Irregular Low Density Parity Check Codes, Based on Geometry Decomposition and Masking”, submitted to IEEE Trans. Inform. Theory, 2004. [12] G. Hellstern, ”Coded modulation with feedback decoding trellis codes”, in Proc. IEEE Int. Conf. on Communications, Geneva, Switzerland, May 1993, pp. 1071-1075. [13] G. Ungerboeck, ”Channel coding with multilevel/phase signals”, IEEE Trans. Inform. Theory, vol. IT-28, pp. 55-66, Jan. 1982. [14] Yeong-Luh Ueng, Chia-Jung Yeh, and Mao-Chao Lin, ”On trellis codes with a delay processor and a signal mapper”, IEEE Trans. on Comm. wol. 50, No. 12, pp.1906-1917, Dec. 2002. [15] Chia-Jung Yeh, ”Further study on multilevel turbo coded modulation using a delay processor”, thesis, National Taiwan University, Taipei, Taiwan, 2000. [16] Stephan ten Brink, Joachim Speidel, and Ran-Hong Yan, ”Iterative demapping and decoding for multilevel modulation”, Global Telecommunications Conference, 1998. GLOBECOM 98. The Bridge to Global Integration. IEEE Volume 1, 8-12 Nov. 1998 Page(s):579 - 584 vol.1 [17] C. Berrou, A. Glavieux, P. Thitimajshima, ”Near shannon limit error-correcting coding and decoding: Turbo-codes”, Proc. ICC’93, Geneva, Switzerland, May 1993, pp. 1064-1070. [18] G. A. Margulis, ”Explicit construction of graphs without short cycles and kow density codes”, Combibatorica, vol.2, no.1, pp. 71-78, 1982. [19] Xiumei Yang, Dongfeng Yuan, Piming Ma, and Mingyan Jiang; ”New research on unequal error protection (UEP) property of irregular LDPC codes”, Consumer Communications and Networking Conference, 2004. CCNC 2004. First IEEE 5-8 Jan. 2004 Page(s):361 - 363. [20] Pishro-Nik, H., Rahnavard, N., and Fekri, F., ”Results on non-uniform error correction using low-density parity-check codes”, Global Telecommunications Conference, 2003. GLOBECOM ’03. IEEE Vol. 4, 1-5 Dec. 2003 Page(s):2041 - 2045 vol.4 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/38093 | - |
dc.description.abstract | 根據以往之研究,我們知道迴旋碼 (Convolutional code) 跟隨延遲處理器 (A delay processor) 及信號點對應器 (A Signal mapper) 的組合能建構出具有大自由距離的迴旋碼。所以很自然的把延遲處理器及信號點對應器的組合應用到低密度同位檢查 (Low-density parity check, LDPC) 碼上試圖達到更大的自由距離。
根據我們提出的架構,我們設計一個兩層的延遲處理器及兩種不同的解碼方法,分別是介紹在4.2節的原始解碼器 (Original decoder) 及5.1節的遞迴解碼器 (Iterative decoder)。模擬結果顯示使用原始解碼器去解兩層的延遲處理器,其結果從中到高訊雜比效能皆不錯,但是在訊雜比低時,會有錯誤蔓延 (Error Propagation) 的問題產生而導致效能很差。因此我們提出遞迴解碼器去解決此問題,而模擬的結果顯示使用遞迴解碼器不但能改善錯誤率從中到高訊雜比,而且於低訊雜比的部分也能有改善 | zh_TW |
dc.description.abstract | As indicated in [12], we observe that a delay processor and a signal mapper following the encoder of a convolutional code C can result in a convolutional code C of large free distances. It is natural to consider once again applying a delay processor and a signal mapper to the output of the low-density parity check (LDPC) code to achieve large free distance.
With the proposed scheme, we show a design for a 2-level delay processor. And we proposed two decoding methods, ”original decoder” and ”iterative decoder”, in sec. 4.2 and sec. 5.1, respectively. Simulation results show that the performance of a 2-level delay processor with original decoder is good at moderate to high SNRs, but poor at low SNR owing to the problem of the error propagation. To overcome this problem, iterative decoder was proposed. Simulation results show that the performance of a 2-level delay processor with iterative decoder is good not only at moderate to high SNR, but also at low SNR. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T16:26:19Z (GMT). No. of bitstreams: 1 ntu-94-R92942037-1.pdf: 806908 bytes, checksum: 12c699aea5a02bc570c5d0775a6ff19d (MD5) Previous issue date: 2005 | en |
dc.description.tableofcontents | 1 Introduction 1
2 Reviews on LDPC Codes 3 2.1 Representation of LDPC codes . . .. . . . . . . . . . 3 2.2 EncodingMethods . . . . . . . . . . . . . . . . . . . 6 2.3 DecodingMethods . . . . . . . . . . . . . . . . . . . 7 2.3.1 Gallager’s hard-decision decoding [1] . . . . . . 7 2.3.2 Sumproduct algorithm(SPA) . . . . . . . . . . . . . 8 3 Some LDPC Code Constructions 11 3.1 Regular LDPC Codes . . . . . . . . . . . . . . . . 11 3.1.1 Gallager’s Codes . . . . . . . . . . . . . . . . 11 3.1.2 Mackay’s Codes . . . . . .. . . . . . . . . . . . 12 3.1.3 Finite Geometries LDPC Codes . . . . . . . . . . . 13 3.2 Irregular LDPC Codes . . . . . . . . . . . . . . . . 20 3.3 Construction of Irregular LDPC Codes Based on Masked EG-Gallager LDPC codes[11] . . . . . . . . . . . . . . . 21 4 LDPC Codes with Inter-block Memories 32 4.1 A Delay Processor Scheme . . . . . . . . . . . . . . 33 4.2 Combine LDPC Codes with a Delay Processor Scheme . . 35 4.3 Simulations . . . . . . . . . . . . . . . . . . . . . . .38 4.4 A Modified Encoding and Decoding System . . . . . . . 45 5 Iterative Decoding for LDPC Codes with a Delay Processor Scheme 47 5.1 The Proposed Iterative Coding Scheme . . . . . . . . 47 5.2 Simulations . . . . . . . . . . . . . . . . . . . . . . 52 6 Conclusions 57 A Some Detail of the simulation 58 | |
dc.language.iso | en | |
dc.title | 具區塊記憶之LDPC編碼 | zh_TW |
dc.title | LDPC Coding with Inter-block Memories | en |
dc.type | Thesis | |
dc.date.schoolyear | 93-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 蘇賜麟,趙啟超,蘇育德,呂忠津 | |
dc.subject.keyword | 低密度同位檢查碼,延遲處理器,遞迴解碼器, | zh_TW |
dc.subject.keyword | LDPC,Delay processor,Iterative decoder, | en |
dc.relation.page | 62 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2005-07-15 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
顯示於系所單位: | 電信工程學研究所 |
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