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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/37801完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭正邦 | |
| dc.contributor.author | Hung-Che Hsieh | en |
| dc.contributor.author | 謝宏哲 | zh_TW |
| dc.date.accessioned | 2021-06-13T15:44:32Z | - |
| dc.date.available | 2013-07-07 | |
| dc.date.copyright | 2008-07-07 | |
| dc.date.issued | 2008 | |
| dc.date.submitted | 2008-07-02 | |
| dc.identifier.citation | [1] P. C. Fazan and V. K. Mathews, “A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMs,” IEDM Dig.,, 57-60 (1993).
[2] Taurus TSUPREM-4 User Guide, Synopsys Inc., Mountain View, CA, 146 Oct. 2005. [3] R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,” in IEDM Tech. Dig., 2002, pp. 117–120. [4] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, R. Gwoziecki, S. Orain, E. Robilliart, C. Raynaud, and H. Dansas, “Electrical Analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress,” IEEE Trans. Electron Devices, vol. 51, no. 8, pp. 1254–1261, Aug. 2004. [5] J. Pretet, D. Ioannou, N. Subba, S. Cristoloveanu, W. Maszara, and C. Raynaud, “Narrow-channel effects and their impact on the static And floating-body characteristics of STI- and LOCOS-isolated SOI MOSFETs,” Solid State Electron., vol. 46, no. 11, pp. 1699–1707,Nov. 2002. [6] J. Pretet, N. Subba, D. Ioannou, S. Cristoloveanu, W. Maszara, and C. Raynaud, “Reduced floating body effects in narrow channel SOI MOSFETs,” IEEE Electron Device Lett., vol. 23, no. 1, pp. 55–57, Jan. 2002. [7] Lin I, Su V, Kuo J, Lee R, Lin G, Chen D, Yeh C, Tsai C, Ma M, “Influence of STI-Induced mechanical stress in kink effect of 65nm PD SOI CMOS devices, ” EDSSC 2007; 107-108. [8] I. Lin, V. Su, J. B. Kuo, M. Ma, C. T. Tsai, C. S. Yeh and D. Chen,“STI Mechanical Stress Induced Subthreshold Kink Effect of 40nm PD SOI NMOS Device,” Dig. Of ISDRS, Washington, Dec. 2007. [9] V. C. Su, I. S. Lin, J. B. Kuo, D. Chen, C. S. Yeh, C. T. Tsai and M. Ma, “Shallow Trench Isolation (STI)-Induced Mechanical Stress-Related Kink Effect Behavior of 40nm PD SOI NMOS Device,” to be published in IEEE Trans. Electron Devices, June 2008. [10] Lin IS, Su VC, Kuo JB, Chen D, Yeh CS, Tsai CZ, Ma M, “STI-induced mechanical stress-related kink effect of 40nm PD SOI NMOS devices, ”EUROSOI 2008; 81-82. [11] Taurus Medici User Guide, Synopsys Inc., Mountain View, CA, 144 Oct. 2005. [12] S. Selberherr, Analysis and Simulation of Semiconductor Devices. New York: Springer-Verlag, 1984. [13] J. B. Kuo et al., “Analytical bandgap-narrowing-related current-gain model for BJT devices operating at 77 K,” Solid State Electron., vol. 35, no. 6, pp. 785–790, Jun. 1992. [14] Y. G. Chen, S. Y. Ma, J. B. Kuo and R. W. Dutton, “An Analytical Drain Current Model for Short-Channel FD Ultrathin SOI NMOS Devices,” Solid State Electronics, Vol. 38, pp. 2051-2057, 1995. [15] K. W. Su and J. B. Kuo, “A Non-Local Impact Ionization/Lattice Temperature Model for VLSI Double-Gate Ultrathin SOI NMOS Devices,” IEEE Trans. Electron Devices, Vol. 44, No. 2, pp. 324-330,Feb.1997. [16] J. B. Kuo et al., “Analytical bandgap-narrowing-related current-gain model for BJT devices operating at 77 K,” Solid State Electron., vol. 35, no. 6, pp. 785–790, Jun. 1992. [17] S. Selberherr, Analysis and Simulation of Semiconductor Devices.New York: Springer-Verlag, 1984. [18] E. V. Ploeg, C.T. Nguyen, S. S. Wong and J. D. Plummer, “Parasitic Bipolar Gain in Fully Depleted n-Channel SOI MOSFET’S,” IEEE Trans. Electron Devices, Vol. 41, pp. 970-977, 1994. [19] J. Y. Choi, J. G. Fossum, “Analysis and Control of Floating-Body Bipolar Effects in Fully Depleted Submicormeter SOI MOSFET’S,” IEEE Trans. Electron Devices, Vol. 38, pp. 1384-1391, 1991. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/37801 | - |
| dc.description.abstract | 在本論文中，描述使用淺壕溝隔離技術(shallow trench isolation)之40奈米部份解離絕緣體上矽金氧半元件(partially-depleted silicon on isulator device)考慮元件內部機械壓力(mechanical stress)下之電源導通暫態分析(turn-on transient analysis) 。
第一章中介紹絕緣體上矽金氧半(SOI)元件及其元件特性，並對淺壕溝隔離法(STI)及使用淺壕溝隔離法所引起之元件內部機械壓力進行探討。 在第二章將討論在不同的元件內部機械壓力下，部分解離絕緣體上矽金氧半元件在不同的上升時間(rise-time)下，其暫態的分析。利用二維元件模擬器分析元件之汲極電流隨著時間的變化及元件之基體-源極電壓(body-source voltage；Vbs)分析元件內部之導通特性與元件內部寄生雙載子電晶體(parasitic bipolar transistor)之導通情形，分析在不同元件內部機械壓力下，元件的暫態特性與導通情形。 第三章將討論在不同的元件內部機械壓力及不同的溫度下，部分解離絕緣體上矽N型金氧半元件的磁滯現象。 第四章為論文總結，整理在不同的元件內部機械壓力下，部份解離絕緣體上矽金氧半元件之元件內部導通情形，加以討論。 | zh_TW |
| dc.description.abstract | This thesis reports the analysis of the turn on transient and hysteresis behavior of 40 nanometers PDSOI device consider the STI induce mechanical stress。
Chapter 1 introduces the characteristic of the SOI Device and the shallow trench isolation（STI）induce mechanical stress。 Chapter 2 discuss PDSOI turn-on transient analysis considering the different mechanical stress effect，based on the 2D simulation。 Chapter 3 discuss PDSOI hysteresis behavior considering the different mechanical stress effect and different temperature effect。 Chapter 4 is conclution。 | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T15:44:32Z (GMT). No. of bitstreams: 1 ntu-97-R95943146-1.pdf: 3080638 bytes, checksum: 315370787fd4fe9853c03fde46b1a54c (MD5) Previous issue date: 2008 | en |
| dc.description.tableofcontents | 致 謝 4
中文摘要 5 ABSTRACT 6 圖目錄 9 Chapter1 12 1.1絕緣體上矽金氧半元件 13 1.2 部份解離與完全解離絕緣體上矽金氧半元件 15 1.3淺壕溝隔離(shallow trench isolation；STI) 17 1.4淺壕溝隔離造成之元件內部機械壓力 21 1.5結論 22 Chapter 2 24 PDSOI元件之turn-on暫態分析 24 2.1簡介 24 2.2 Turn-on Transient Analysis 25 2.2.1 Rise-time=1ns 26 2.2.2 Rise-time=10ns 29 2.2.3 Rise-time=1ns與Rise-time=10ns的比較 31 2.2.4 Turn-on Transient Analysis 31 2.3撞擊游離(impact ionization)模型考慮能隙縮小(bandgap narrowing)與否之暫態分析 33 2.3.1 Rise-time=1ns 34 2.3.2 Rise-time=10ns 36 2.3.3 Turn-on Transient Analysis 38 2.4 週期性Turn-on-Turn-off Transient Analysis 40 2.4.1上升時間及下降時間皆為1ns，工作週期為4ns 40 2.4.2上升時間及下降時間皆為10ns，工作週期為40ns 43 2.5結論 45 Chapter 3 46 磁滯現象 46 3.1簡介 46 3.2不同的機械壓力影響下之磁滯現象 46 3.3不同的溫度影響下元件的磁滯現象 52 3.4結論 55 Chapter 4 56 總結 56 參考文獻 59 Reference 59 | |
| dc.language.iso | zh-TW | |
| dc.title | 使用二維模擬器分析部份解離絕緣體上矽金氧半元件之電源導通暫態效應及磁滯現象 | zh_TW |
| dc.title | Turn-on Transient Analysis and Hysteresis Behavior of PD SOI MOS Devices Using 2D simulation | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 96-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 蔡成宗,陳正雄,林浩雄,林吉聰 | |
| dc.subject.keyword | 電源導通暫態分析,磁滯現象, | zh_TW |
| dc.subject.keyword | Turn-on Transient Analysis,Hysteresis, | en |
| dc.relation.page | 61 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2008-07-03 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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