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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電子工程學研究所
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/37595
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dc.contributor.advisor陳少傑(Sao-Jie Chen)
dc.contributor.authorHsin-Hsien Yehen
dc.contributor.author葉信顯zh_TW
dc.date.accessioned2021-06-13T15:34:12Z-
dc.date.available2013-08-17
dc.date.copyright2011-08-17
dc.date.issued2011
dc.date.submitted2011-08-10
dc.identifier.citation[1] S. Kumar, A. Jantsch, J.P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani, 'A Network on Chip Architecture and Design Methodology,' in Proceedings of IEEE Computer Society Annual Symposium on VLSI, pp. 105-112, Apr. 2002.
[2] W.J. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004.
[3] G.DeMicheli and L. Benini, Networks on Chips, Morgan Kaufmann, 2006.
[4] R. Marculescu, U.Y. Ogras, L.S. Peh, N.E. Jerger, and Y. Hoskote, 'Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, pp. 3-21, Jan. 2009.
[5] L. Benini and G. De Micheli, 'Network on Chip: A New Paradigm for Systems on Chips Design,' in Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pp. 418-419, Aug. 2002.
[6] Semiconductor Association, The International Technology Roadmap for Semiconductors, 2005.
[7] S. Pasricha and N. Dutt, On-Chip Communication Architectures: System on Chip Interconnect, Morgan Kaufmann, 2008.
[8] P. Guerrier and A. Greiner, 'A Generic Architecture for On-Chip Packet-Switched Interconnections,' in Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pp. 250-256, Mar. 2000.
[9] W.J. Dally and B. Towles, 'Route Packets, Not Wires: On-Chip Interconnection Networks,' in Proceedings of Design Automation Conference, pp. 684-689, Jun. 2001.
[10] J. Duato, S. Yalamanchili and L. Ni, Interconnection Networks - An Engineering Approach, Morgan Kaufmann, 2003.
[11] C.J. Glass and L.M. Ni, 'Adaptive Routing in Mesh-connected Networks,' in Proceedings of the 12th International Conference on Distributed Computing Systems, pp. 12-19, Jun. 1992.
[12] G.M. Chiu, 'The Odd-Even Turn Model for Adaptive Routing,' IEEE Transactions on Parallel and Distributed Systems, vol. 11, pp. 729-738, Jul. 2000.
[13] G. Michelogiannakis, D. Sanchez, W.J. Dally, and C. Kozyrakis, 'Evaluating Bufferless Flow Control for On-Chip Networks,' in Proceedings of the Fourth ACM/IEEE International Symposium on Networks-on-Chip, pp. 9-16, May 2010.
[14] W.J. Dally, 'Virtual-Channel Flow Control,' IEEE Transactions on Parallel and Distributed Systems, vol. 3, pp. 194-205, Aug. 1992.
[15] J. Hu and R. Marculescu, 'Application-Specific buffer Space Allocation for Networks-on-Chip Router Design,' in Proceedings of International Conference on Computer Aided Design, pp. 354-361, Nov. 2004.
[16] X. Chen and L.S. Peh, 'Leakage Power Modeling and Optimization in Interconnection Networks,' in Proceedings of Low Power Electronics and Design, pp. 90-95, Sep. 2003.
[17] Y.C. Lan, S.H. Lo, Y.C. Lin, Y.H. Hu, and S.J. Chen, 'BiNoC: A Bidirectional NoC Architecture with Dynamic Self-Reconfigurable Channel,' in Proceedings of the 3rd ACM/IEEE International Symposium on Network-on-Chip, pp. 266-275, May 2009.
[18] Y.C. Lan, H.A. Lin, S.H. Lo, Y.H. Hu, and S.J. Chen, 'A Bidirectional NoC (BiNoC) Architecture with Dynamic Self-Reconfigurable Channel,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, pp. 427-440, Mar. 2011.
[19] M. Karol, M. Hluchyj, and S. Morgan, 'Input Versus Output Queueing on a Space-Divison Packet Switch,' IEEE Transactions on Communications, vol. 35, pp. 1347-1356, Dec. 1987.
[20] Y. Tamir and G. L. Frazier, 'High-Performance Multi-Queue Buffers for VLSI Communication Switches,' in Proceedings of the 15th Annual International Symposium on Computer Architecture, pp. 343-354, May 1988.
[21] M. Rezazad and H. Sarbazi-azad, 'The Effect of Virtual Channel Organization on the Performance of Interconnection Networks,' in Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium, April 2005.
[22] C. A. Nicopoulos, D. Park, J. Kim, N. Vijaykrishnan, M. S. Yousif, and C. R. Das, 'ViChaR: A Dynamic Virtual Channel Regulator or Network-on-Chip Routers,' in Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 333-346, Dec. 2006.
[23] M. Lai, L. Gao, W. Shi, and Z. Wang, 'Escaping from Blocking: a Dynamic Virtual Channel for Pipelined Routers,' in Proceedings of Complex, Intelligent and Software Intensive System, pp. 795-800, Mar. 2008.
[24] M. Lai, Z. Wang, L. Gao, H. Lu, and K. Dai, 'A Dynamically-Allocated Virtual Channel Architecture with Congestion Awareness for On-Chip Routers,' in Proceedings of Design Automation Conference (DAC 2008), pp. 630-633, Jun. 2008.
[25] M.H. Neishaburi and Z. Zilic, 'Reliability Aware NoC Router Architecture Using Input Channel Buffer Sharing,' in Proceedings of the 19th ACM Great Lakes Symposium on VLSI, pp. 511-516, May 2009.
[26] D.C. Gazis, Traffic Science, John Wiley & Sons, 1974.
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/37595-
dc.description.abstract在網路晶片架構中,緩衝器 (Buffer) 的大小一直是影響電路在效能、面積、功耗表現上的主要對象之一。如何分配緩存資源便成為相關設計上一個重要的議題。為了能更有效利用緩存資源,在該論文中我們提出一個具有虛擬通道 (Virtual-Channel) 共享機制的雙向通道網路晶片架構;此架構允許網路晶片路由器內不同傳輸方向在閒置時將其所屬的虛擬通道資源分享給相鄰的傳輸方向使用,達到緩解負載流量的目的。透過該共享機制可以有效的提高路由器內緩存資源的利用率,改善網路晶片在負載不平衡狀況下的傳輸效能。本文利用一個精準時脈週期的測試環境進行模擬,從模擬結果可看出具有虛擬通道共享機制之雙向通道網路晶片相對於傳統虛擬通道分配機制之雙向通道網路晶片架構在效能與資源利用率上佔有一定的優勢。zh_TW
dc.description.abstractNetwork-on-Chip (NoC) architecture has been viewed as a possible solution to support the growing design complexity of Multi-Processor System-on-Chip (MPSoCs) since the advent of deep sub-micron technology in recent years. In an NoC design, buffer resources dominate the major power consumption and area overhead of the entire router architecture. How to utilize buffer resources efficiently is always a significant study issue. In this Thesis, we propose a power- and area-efficient router architecture using a Virtual-Channel Sharing (VCS) mechanism to improve the network performance in a Bi-directional NoC (BiNoC) architecture especially under the non-uniform traffic environment. The underlying idea is that each input port in our proposed router can share its idled virtual-channels to the neighboring input ports. In other words, an input port can borrow idled virtual-channels from the adjacent input ports to suffer the temporary high traffic load. The improvement of the routing and virtual-channel utilization flexibility by our proposed VCS mechanism can eliminate the head-of-line blocking efficiently under a constrained number of virtual-channels. The experimental results show that a significant performance improvement, in terms of area overhead and power consumption, can be obtained by our proposed VCS mechanism.en
dc.description.provenanceMade available in DSpace on 2021-06-13T15:34:12Z (GMT). No. of bitstreams: 1
ntu-100-R98943095-1.pdf: 2533843 bytes, checksum: 5150dc93e81e02c527d01afa446ecf79 (MD5)
Previous issue date: 2011
en
dc.description.tableofcontentsABSTRACT i
LIST OF FIGURES vii
LIST OF TABLES xi
CHAPTER 1 INTRODUCTION 1
1.1 Evolution in On-Chip Interconnection 1
1.2 Concepts of Network-on-Chip 3
1.2.1 Topology 3
1.2.2 Routing 4
1.2.3 Flow Control 4
1.3 Buffer Sizing and Buffer Management 7
1.4 Thesis Organization 9
CHAPTER 2 NETWORK-ON-CHIP ARCHITECTURE 11
2.1 Design of a Network-on-Chip 11
2.2 Basic Router Architecture 12
2.2.1 Input Buffer Unit 14
2.2.2 Routing Computation 14
2.2.3 Virtual-Channel Allocation 16
2.2.4 Switch Allocation 18
2.2.5 Crossbar 19
2.3 Bi-directional Network-on-Chip (BiNoC) 20
CHAPTER 3 PRELIMINARY 23
3.1 Dynamically Allocated Multi-Queue Buffers 24
3.2 Dynamic Virtual-Channel Regulator 26
3.3 Dynamic Virtual-Channel Allocation 29
3.4 Remark 30
CHAPTER 4 VIRTUAL-CHANNEL SHARING MECHANISM 31
4.1 Motivation 31
4.2 Virtual-Channel Sharing Scheme 33
4.3 Constrained Virtual-Channel Allocation for VCS 34
4.3.1 Resource Dependency 35
4.3.2 Constrained Virtual-Channel Allocation 37
CHAPTER 5 ROUTER IMPLEMENTATION 41
5.1 BiNoC-VCS Router Architecture 41
5.2 Virtual-Channel Allocation on BiNoC-VCS 42
5.3 Inter-Router Virtual-Channel Status Synchronization 44
5.3.1 Virtual-Channel Status Synchronization Scheme 46
5.3.2 NVC Reservation Checker 47
5.3.3 Example for VC Allocation Information Synchronization 49
CHAPTER 6 EXPERIMENTAL RESULTS AND DISCUSSION 51
6.1 Performance Evaluation on BiNoC-VCS Routers 52
6.1.1 Simulation-1 for BiNoC platforms with XY Routing Algorithm 54
6.1.2 Simulation-1 for BiNoC platforms with Odd-Even Routing Algorithm 59
6.1.3 Simulation-2 for BiNoC platforms with XY Routing Algorithm 62
6.1.4 Simulation-2 for BiNoC platforms with Odd-Even Routing Algorithm 65
6.2 Performance Evaluation on NoC-VCS Routers 68
6.2.1 Simulation-1 for NoC platforms with XY Routing Algorithm 70
6.2.2 Simulation-1 for NoC platforms with Odd-Even Routing Algorithm 73
6.2.3 Simulation-2 for NoC platforms with XY Routing Algorithm 76
6.2.4 Simulation-2 for NoC platforms with Odd-Even Routing Algorithm 79
6.3 Refusal Rate for Virtual-Channel Demand 82
6.4 Estimation on Implementation Overhead 84
6.5 Performance Evaluation with Different Numbers of NVCs on BiNoC-VCS 87
CHAPTER 7 CONCLUSION 91
REFERENCE 93
dc.language.isoen
dc.title一個具虛擬通道共享機制之雙向通道網路晶片架構設計zh_TW
dc.titleDesign of a Bi-directional NoC Architecture with Virtual Channel Sharing Mechanismen
dc.typeThesis
dc.date.schoolyear99-2
dc.description.degree碩士
dc.contributor.oralexamcommittee黃威(Wei Huang),熊博安(Pao-Ann Hsiung)
dc.subject.keyword網路晶片,路由器,雙向通道,虛擬通道,負載平衡,緩存資源,資源共享,zh_TW
dc.subject.keywordNetwork-on-Chip,NoC,Router,Bidirectional Channel,Virtual-Channel,Load-balance,Buffer,Resource Sharing,en
dc.relation.page95
dc.rights.note有償授權
dc.date.accepted2011-08-10
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept電子工程學研究所zh_TW
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