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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳少傑(Sao-Jie Chen) | |
dc.contributor.author | Deng-Yuan Zheng | en |
dc.contributor.author | 鄭登元 | zh_TW |
dc.date.accessioned | 2021-06-13T15:28:36Z | - |
dc.date.available | 2013-08-20 | |
dc.date.copyright | 2011-08-20 | |
dc.date.issued | 2011 | |
dc.date.submitted | 2011-08-10 | |
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Schonwald, J. Zimmermann, O. Bringmann, and W. Rosenstiel, 'Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures,' in Proc. of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, pp. 527-534, Aug. 2007. [9] A. Kohler, G. Schley, and M. Radetzki, 'Fault Tolerant Network on Chip Switching With Graceful Performance Degradation,' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 6, pp. 883-896, June 2010. [10] Z. Zhen, A. Greiner, and S. Taktak, 'A Reconfigurable Routing Algorithm for a Fault-Tolerant 2D-Mesh Network-on-Chip,' in Proc. of the 45th Design Automation Conference, pp. 441-446, June 2008. [11] D. Fick, A. DeOrio, G. Chen, V. Bertacco, D. Sylvester, and D. Blaauw, 'A Highly Resilient Routing Algorithm for Fault-Tolerant NoCs,' in Proc. of the 12nd Design, Automation and Test in Europe Conference and Exhibition, pp. 21-26, Apr. 2009. [12] Y.C. Lan, S.H. Lo, Y.C. Lin, Y.H. Hu, and S.J. Chen, 'BiNoC: A Bidirectional NoC Architecture with Dynamic Self-Reconfigurable Channel,' in Proc. of the 3rd ACM/IEEE International Symposium on Networks-on-Chip, pp. 266-275, May 2009. [13] Y.C. Lan, H.A. Lin, S.H. Lo, Y.H. Hu, and S.J. Chen, 'A Bidirectional NoC (BiNoC) Architecture with Dynamic Self-Reconfigurable Channel,' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, pp. 427-440, Mar. 2011. [14] M.H. Cho, M. Lis, M. Kinsy, K.S. Shim, T. Wen, and S. Devadas, 'Oblivious Routing in On-Chip Bandwidth-Adaptive Networks,' in Proc. of the 18th International Conference on Parallel Architectures and Compilation Techniques, pp. 181-190, Sep. 2009. [15] M. Cuviello, S. Dey, X. Bai, and Y. Zhao, 'Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects,' in Proc. of the IEEE/ACM International Conference on Computer-Aided Design, pp. 297-303, Sep. 1999. [16] K. V. Anjan and T. M. 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Dick, 'Embedded System Synthesis Benchmark Suites (E3S),' http://ziyang.eecs.umich.edu/~dickrp/e3s/. [22] A.S. Tanenbaum, Computer Networks Forth edition, Pearson Education, Upper Saddle River, NJ, 2002. [23] W. J. Dally and C. L. Seitz, 'The torus routing chip,' Distributed Computing, Vol. 1, No. 4, pp. 187-196, 1986. [24] Y.H. Kang, T.J. Kwon, and J. Draper, 'Fault-Tolerant Flow Control in On-Chip Networks,' in Proc. of the 4th ACM/IEEE International Symposium on Networks-on-Chip, pp. 79-86, May 2010. [25] D. Park, C. Nicopoulos, J. Kim, N. Vijaykrishnan, and C.R. Das, 'Exploring Fault-Tolerant Network-on-Chip Architectures,' in Proc. of the International Conference on Dependable Systems and Networks, pp. 94-104, June 2006. [26] S. Murali, T. Theocharides, N. Vijaykrishnan, and M.J. Irwin, L. Benini, and G. DeMicheli, 'Analysis of Error Recovery Schemes for Networks on Chips,' IEEE Design and Test of Computers, Vol. 22, No. 5, pp. 434-442, Oct. 2005. [27] C. Grecu, A. Ivanov, R. Saleh, E.S. Sogomonyan, and P.P. Pande, 'On-Line Fault Detection and Location for NoC Interconnects,' in Proc. of the 12nd IEEE International On-Line Testing Symposium, pp. 145-150, July 2006. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/37451 | - |
dc.description.abstract | 本文提出了一個運用雙向傳輸通道之容錯網路晶片設計,使得網路晶片可以避免靜態或是動態的錯誤傳輸通道,而繼續正常的傳輸溝通。在傳統的網路晶片平台,錯誤的傳輸通道會造成傳輸資料的堵塞或是繞道,進而造成效能上嚴重的影響。這篇論文提出了一個運用可動態調整之雙向傳輸通道的容錯機制,根據所實現的錯誤偵測和診斷機制,使得網路晶片可以精確的避開錯誤通道,且僅伴隨著輕微的效能影響。潛在的效能優勢像是故障率的降低和可靠度的增加也都在本文中仔細的分析。實驗結果說明了在錯誤發生的網路狀態下,對此容錯機制的效能影響不論是在合成交通型態或真實交通型態都是輕微的。除了避免錯誤之外,這篇論文也提出了一個以封包大小為單位的蟲洞交換重傳機制,在網路晶片的資料鏈結層來處理網路晶片發生錯誤的當下而受損害的傳輸資料。實驗結果也分析了在不同的錯誤狀況底下,錯誤對重傳機制的效能變化。 | zh_TW |
dc.description.abstract | A Bidirectional Fault-Tolerant NoC (BFT-NoC) design capable of mitigating both static and dynamic channel failures is proposed. In a traditional NoC platform, a faulty data channel will force blocked packets to make costly detours, resulting in significant performance hits. In this Thesis, novel fault-tolerance measures for a bidirectional NoC platform are proposed. A fault detection and diagnosis mechanism is implemented to determine the fault condition. According to the detected fault condition, the BFT-NoC scheme with reconfigurable bidirectional channels offers great flexibility to sustain data-link faults while incurring negligible performance loss. Potential performance advantages in terms of failure rate reduction and Reliability enhancement of the BFT-NoC architecture are carefully analyzed. Extensive experimental results clearly validate the fault-tolerance performance of BFT-NoC at both synthetic and real world network traffic patterns. In addition to fault avoidance, a packet-basis retransmission mechanism with wormhole switching is investigated to deal with the damaged data caused by the faults. The retransmission performance variation in different fault conditions is also analyzed with the experimental results. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T15:28:36Z (GMT). No. of bitstreams: 1 ntu-100-R98943094-1.pdf: 2079771 bytes, checksum: a1821ca3e57f06e5cf57f16c79f2f615 (MD5) Previous issue date: 2011 | en |
dc.description.tableofcontents | ABSTRACT i
LIST OF FIGURES vii LIST OF TABLE xi CHAPTER 1 INTRODUCTION 1 1.1 Basic Concept of Network-on-Chip 1 1.1.1 Topology 2 1.1.2 Routing 3 1.1.3 Performance Evaluation 4 1.1.3.1 Latency 5 1.1.3.2 Throughput 5 1.1.3.3 Interactions between Latency and Throughput 5 1.2 Fault-Tolerance 6 1.3 Contributions of this Thesis 6 1.4 Thesis Organization 7 CHAPTER 2 PRELIMINARIES AND MOTIVATION 9 2.1 Fault Detection and Diagnosis in NoCs 10 2.2 Fault-Tolerance in NoCs 11 2.2.1 Problem Formulation 11 2.2.2 Fault-Tolerant Routing Algorithm 13 2.3 Bidirectional Channel in NoCs 15 2.4 Motivation 16 CHAPTER 3 FAULT DETECTION AND DIAGNOSIS IMPLEMENTATION 19 3.1 Fault Detection Mechanism 19 3.1.1 CRC Theory 20 3.1.2 CRC Implementation 21 3.2 Fault Diagnosis Mechanism 23 3.3 Fault Detection and Diagnosis on Bidirectional Channel 26 CHAPTER 4 BIDIRECTIONAL FAULT-TOLERANT NOC SCHEME 29 4.1 Introduction of our Fault-Tolerant NoC Scheme 29 4.2 Bidirectional Fault-Tolerant NoC 31 4.3 Fault-Tolerance Measures 33 4.3.1 Fault-Tolerance Control Procedure 34 4.3.2 In-Router Deadlock and its Solution 35 4.3.3 Combination with other Fault-Tolerant Algorithms 38 4.4 Enhancements in Failure Rate and Reliability 38 4.4.1 Failure Rate Reduction 38 4.4.2 Reliability Enhancement 40 4.5 BFT-NoC Experimental Results 42 4.5.1 Experiments with Synthetic Traffics 43 4.5.2 Experiments with Real Traffics 46 4.5.3 Implementation Overhead 47 CHAPTER 5 RETRANSMISSION MECHANISM 49 5.1 Bidirectional Router and its Retransmission Architectures 49 5.2 Proposed Retransmission Mechanism 51 5.2.1 Store-and-Forward Switching and Wormhole Switching 52 5.2.2 Packet-Basis Retransmission Scheme with Wormhole Switching 53 5.2.3 Buffer Management for Packet Retransmission 55 5.3 Retransmission Mechanism Experimental Results 57 5.3.1 Experiments Setting 57 5.3.2 Performance Comparisons between Retransmission Mechanisms based on Store-and-Forward Switching and Wormhole Switching 58 5.3.3 Performance Analyses among Different Flit-Error-Rates 60 5.3.4 Performance Analyses among Different Faulty-Channel Numbers 63 5.3.5 Performance Analyses in Real Traffic Patterns 66 5.3.6 Implementation Overhead 67 CHAPTER 6 CONCLUSION 69 REFERENCE 71 | |
dc.language.iso | en | |
dc.title | 運用雙向傳輸通道之容錯網路晶片設計 | zh_TW |
dc.title | Fault-Tolerant NoC Design Using Bidirectional Channel | en |
dc.type | Thesis | |
dc.date.schoolyear | 99-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃威(Wei Huang),熊博安(Pao-Ann Hsiung) | |
dc.subject.keyword | 網路晶片,錯誤容忍,重傳,可靠度,雙向傳輸通道, | zh_TW |
dc.subject.keyword | NoC,Fault-Tolerance,Retransmission,Reliability,Bidirectional Channel, | en |
dc.relation.page | 73 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2011-08-11 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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