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標題: | 應用於穿戴式裝置之極低電壓無線收發機 Ultra-low-voltage Wireless Transceiver for Wearable Applications |
作者: | Tse-Wei Wang 王則惟 |
指導教授: | 林宗賢(Tsung-Hsien Lin) |
關鍵字: | 穿戴式裝置,低功耗,無線收發機,低電壓,注入式技巧,差動式二元相位偏移, Wearable applications,Low power consumption,Wireless transceiver,Injection-locking technique,D-BPSK, |
出版年 : | 2016 |
學位: | 碩士 |
摘要: | 穿戴型裝置近年來已經成為全球業界與消費者熱烈關切的議題。為了達到長時間操作的目的,低功率消耗將會是電路設計上最主要的考量之一。對於負責處理傳送/接收訊號的無線收發機來說,更會是設計上的一大挑戰。
本論文提出了一個具有高能量效率,操作在0.5V供應電壓環境下,使用注入式鎖定技巧之低功耗高效能無線收發機,調變方面採用差動式二元相位偏移(D-BPSK)。 接收機部分主要是利用注入式鎖定的技巧,當接收之輸入訊號相位產生變化時,震盪器的輸出振幅會產生暫時性的改變,即相位變化將透過注入式鎖定技巧轉換為震盪器的振幅變化來完成解調。此架構不需閉迴路系統來完成相位同步,可大幅簡化系統架構,進而降低功率消耗。本作品使用台積電0.18微米製程,系統功耗為0.97毫瓦,靈敏度為-45dBm,最大資料傳輸量為10 Mbps,在此資料傳輸量下能量效率為97 pJ/b。 發送機部分也是利用注入式鎖定技巧,低頻相位資訊會經由相位選擇器選取後注入高頻振盪器,當低頻的相位發生改變,高頻振盪器便會重新鎖定並且改變相位來完成調變。此架構因為不需產生高頻多相位的振盪訊號,因此可有效降低整體功率消耗。本作品使用台積電0.18微米製程之模型來進行模擬,整體系統功耗為0.297毫瓦,最大輸出功率為-9.7dBm,能量效率為29.7 pJ/b,最大資料傳輸量為10 Mbps,在此資料傳輸量下誤差向量幅度為13%。 Wearable devices have been popular issues in recent years. Low power consumption is an important design target for the purpose of long-time usability. It’s also an enormous challenge for wireless transceivers circuit design. This thesis proposes an energy-efficient injection-locked transceiver which operates at 0.5V voltage supply. The D-BPSK modulation and demodulation are adopted for this system. The proposed receiver adopts injection-locked technique to demodulate received data. The injection-locked oscillator detects the input phase information and reacts on its output amplitude. In this receiver, the closed loop topology is not required for phase synchronization, which simplifies receiver design and reduce power consumption. This work is fabricated in TSMC 0.18-μm CMOS technology. The total power consumption is 0.97 mW with the sensitivity is -45 dBm at 10-Mbps data rate. The equivalent energy efficiency is 97 pJ/b. The injection-locked technique is adopted in the transmitter design to modulate date. The injection locked oscillator will re-lock to a new phase when the phase changes at low frequency carrier. High frequency multi-phase oscillator is not required in this architecture; therefore it will reduce total power consumption significantly. This work is simulated under TSMC 0.18-μm CMOS technology. The total simulated power consumption is 0.297 mW with 13% EVM at 10-Mbps data rate. The maximum output power is -9.7 dBm, and the energy efficiency is 29.7 pJ/b. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/3741 |
DOI: | 10.6342/NTU201602538 |
全文授權: | 同意授權(全球公開) |
顯示於系所單位: | 電子工程學研究所 |
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