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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 張耀文(Yao-Wen Chang) | |
dc.contributor.author | Chen-Wei Liu | en |
dc.contributor.author | 劉振偉 | zh_TW |
dc.date.accessioned | 2021-06-13T08:17:11Z | - |
dc.date.available | 2005-07-30 | |
dc.date.copyright | 2005-07-30 | |
dc.date.issued | 2005 | |
dc.date.submitted | 2005-07-19 | |
dc.identifier.citation | [1] J. R. Black. “Electromigration failure modes in aluminum metallization for
semicondutor devices,” Proc. of IEEE, pp. 1587, 1969. [2] J. A. Carballo and J. L. Burns, S.-M. Yoo, I. Vo, and V. R. Norma. “A semicustom voltage-island technique and its application to high-speed serial links,” in Proc. of ACM/IEEE International Symposium on Low Power Electronic Design , pp. 60–65, 2003. [3] Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu. “B*-trees: A new representation for non-slicing floorplans,” in Proc. ACM/IEEE Design Au- tomation Conference, pp. 458–463, 2000. [4] H. Chen, C.-K. Cheng, A. B. Kahng, M. Mori and Q. Wang. “Optimal planning for mesh-based power distribution,” in Proc. of ACM/IEEE Asia South Pacific Design Automation Conference, pp. 444–449, 2004. [5] T.-H. Chen and C. C.-P. Chen. “Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods,” in Proc. ACM/IEEE Design Automation Conference, pp. 559–562, 2001. [6] S. Chowdhury. “Optimum design of reliable ic power networks having general graph topologies,” in Proc. ACM/IEEE Design Automation Conference, pp. 787–790, 1989. [7] T. H. Cormen, C. E. Leiserson, and R. L. Rivest. Introduction to algorithms, MIT, 1990. [8] A. Dharchoudhury, R. Panda, D. Blaauw, R. Vaidyanathan, B. Tutuianu, and D. Bearden. “Design and analysis of power distribution networks in PowerPC microprocessors,” in Proc. ACM/IEEE Design Automation Conference, pp. 738–743, 1998. [9] G. H. Golub and v. L. Charles F. Matrix Computations, Johns Hopkins University, 1996. [10] P.-N. Guo, C.-K. Cheng, and T. Yoshimura. “An O-tree representation of non-slicing floorplan and its applications,” in Proc. ACM/IEEE Design Au- tomation Conference, pp. 268–273, 1999. [11] Shih-Hsu Huang and Chu-Liao Wang. “An Effective Floorplan-Based Power Distribution Network Design Methodology Under Reliability Constraints” in Proc. of IEEE International Symposium on Circuits and Systems , pp. 353-356, 2002. [12] J. Hu, Y. Shin, N. Dhanwada, and R. Marculescu. “Architecting voltage islands in core-based system-on-chip designs,” in Proc. of ACM/IEEE Interna- tional Symposium on Low Power Electronic Design, pp. 180–185, 2004. [13] D. Kouroussis and F. N. Najm. “A static pattern-independent technique for power grid voltage integrity verification,” in Proc. ACM/IEEE Design Au- tomation Conference, pp. 99–104, 2003. [14] J. N. Kozhaya, S. R. Nassif, and F. N. Najm. “Multigrid-like technique for power grid analysis,” in Proc. of ACM/IEEE International Conference on Computer-Aid Design, pp. 480–487, 2001. [15] OpenRISC project, http://www.opencores.org/. [16] J.-M. Lin, H.-E. Yi, and Y.-W. Chang. “Module placement with boundary constraints using B*-trees,” IEE Proc.s–Circuits, Devices and Systems, Vol. 149, No. 4, pp. 251–256, August 2002. [17] S. Lin and N. Chang. “Challenges in power-ground integrity,” in Proc. of IEEE International Conference on Computer Design, pp. 651–654, 2001. [18] V. Litovski and M. Zwolinski. VLSI Circuit Simulation and Optimization, Chapman & Hall, 1997. [19] T. Mitsuhashi and E. S. Kuh. “Power and ground network topology optimization for cell based VLSIs,” in Proc. ACM/IEEE Design Automation Confer- ence, pp. 524–529, 1992. [20] H. Murata and E. S. Kuh. “Sequence-pair based placement method for hard/soft/pre-placed modules,” in Proc. ACM International Symposium on Physical Design, pp. 167–172, 1998. [21] J. Singh and S. S. Sapatnekar. “Topology optimization of structured power/ground networks,” in Proc. ACM International Symposium on Physical Design, pp. 116–123, 2004. [22] Source code, http://cc.ee.ntu.edu.tw/˜ywchang/research.html. [23] K. Wang and M. Marek-Sadowska. “On-chip power supply network optimization using multigrid-based technique,” in Proc. ACM/IEEE Design Automa- tion Conference, pp. 113–118, 2003. [24] D. F. Wong and C. L. Liu. “A new algorithm for floorplan design,” in Proc. ACM/IEEE Design Automation Conference, pp. 101–107, 1986. 42 [25] S.-W. Wu and Y.-W. Chang. “Efficient power/ground network analysis for power integrity-driven design methodology,” in Proc. ACM/IEEE Design Au- tomation Conference, pp. 177–180, 2004. [26] J.-S. Yim, S.-O. Bae, and C.-M. Kyung. “A floorplan-based planning methodology for power and clock distribution in ASICs,” in Proc. ACM/IEEE Design Automation Conference, pp. 766–771, 1999. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/36812 | - |
dc.description.abstract | 摘要
隨著製程的進步,金屬導線線寬(metal width)變窄而導線長度總和(global wire length)增加,這樣的趨勢造成電源供應導線(power wire)的電阻(resistance)增加。更甚於此,工作電壓(threshold voltage)隨製程縮小產生非線性的變化,造成工作電壓跟電源供應電壓(power supply voltage)的比例以及電源供應網路(Power/Ground network)的電壓降(IR drop)成為非常重要的議題,傳統的電源供應網路分析方法通常需要耗費大量時間來計算,並不適用於平面規劃(floorplan)與電源供應網的共同合成上,為了達成共同合成的目的,我們不僅需要速度夠快且有效的平面規劃演算法(algorithm),也需要有效率且不失精準的電源供應網路分析方法,在這論文中,我們將說明我們的共同合成演算法,這個演算法使用了快速的電源供應網分析法以及B*-tree平面規劃演算法,並且整合在業界的設計流程(design flow)中。我們在實際的晶片以及MCNC benchmark上進行實驗,實驗結果顯示我們的設計方法可以在早期的設計流程中修正電源供應網路的問題,達成一次完成的設計流程。 | zh_TW |
dc.description.abstract | As technology advances, the metal width decreases while the global wire length in-
creases. This trend makes the resistance of the power wire increase substantially. Further, the threshold voltage scales nonlinearly, raising the ratio of the threshold voltage to the supply voltage and making the voltage (IR) drop in the power/ground (P/G) network a serious problem in modern IC design. Traditional P/G network analysis methods are often very computationally expensive, and it is thus not feasi- ble to co-synthesize P/G network with floorplan. To make the co-synthesis feasible, we need not only an efficient, effective, and flexible floorplanning algorithm, but also a very efficient, yet sufficiently accurate P/G network analysis method. In this thesis, we present a method for floorplan and P/G network co-synthesis based on an efficient P/G network analysis scheme and the B*-tree floorplan representation. We integrate the co-synthesis into a commercial design flow to develop an effective power integrity (IR-drop) driven design methodology. Experimental results based on a real-world circuit design and the MCNC benchmarks show that our design method- ology successfully fixes the IR-drop errors earlier at the floorplanning stage and thus enables the single-pass design convergence. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T08:17:11Z (GMT). No. of bitstreams: 1 ntu-94-R92943073-1.pdf: 1051117 bytes, checksum: 05a9eace1968de44239ff9e25c6b8206 (MD5) Previous issue date: 2005 | en |
dc.description.tableofcontents | Abstract (Chinese) i
Abstract ii List of Tables v List of Figures vi Chapter 1. Introduction 1 1.1 Related Previous Work 2 1.1.1 Dharchoudhury’s Design Flow 3 1.1.2 Yim’s Floorplan-based P/G Network Planning Methodology 4 1.1.3 Haung and Wang’s Floorplan-Based Power Distribution Network Design Methodology 5 1.1.4 Wu and Chang’s Work 5 1.2 Our Contributions 7 1.3 Organization of the Thesis 8 Chapter 2. Problem Formulation 9 2.1 Notations for Describing Power/Ground Network 9 2.2 Power/Ground Integrity Constraints 9 Chapter 3. The Proposed Design Flow 11 Chapter 4. Floorplan and P/G Network Co-synthesis 14 4.1 P/G Mesh Generation 16 4.2 Macro Current Source Modelling 17 4.3 P/G Networks Analysis 18 4.3.1 P/G Network Estimation 20 4.4 P/G Network Co-synthesis Heuristic 22 4.5 Feasible B*-trees with Power Mesh Constraints 23 4.6 The Co-Synthesis Algorithm 27 Chapter 5. Experimental Results 30 5.1 OpenRISC1200 30 5.2 MCNC benchmark 33 Chapter 6. Conclusion and Future Work 36 6.1 Conclusion 36 6.2 Future Work 37 Bibliography 39 | |
dc.language.iso | en | |
dc.title | 同步平面規劃與電源供應網路共同合成 | zh_TW |
dc.title | Floorplan and Power/Ground Network Co-Synthesis for Fast Design Convergence | en |
dc.type | Thesis | |
dc.date.schoolyear | 93-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林永隆(Youn-Lon Lin),王志恆(J.-H. Wang),黃世旭(Shih-Hsu Huang) | |
dc.subject.keyword | 電源供應網路,平面規劃,設計流程,電壓降, | zh_TW |
dc.subject.keyword | power network,floorplan,design flow,IR-drop, | en |
dc.relation.page | 42 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2005-07-20 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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