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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/36406完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 張時中(Shi-Chung Chuang) | |
| dc.contributor.author | Jen-Hsuan Ho | en |
| dc.contributor.author | 何任軒 | zh_TW |
| dc.date.accessioned | 2021-06-13T07:59:43Z | - |
| dc.date.available | 2014-08-23 | |
| dc.date.copyright | 2011-08-23 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-08-20 | |
| dc.identifier.citation | [1] G.-M. Chen. (2008). The trend of development of semiconductor technology [Online]. Available: http://ctle.cyu.edu.tw/tew/Teacher/data/971223/971223-1.pdf
[2] T. Pomorski, 'Managing Overall Equipment Effectiveness [OEE] to Optimize Factory Performance,' Proc. of 1997 IEEE Intl. Symp. on Semi. Mfg. Conf., Oct. S.F., A33 - A36 [3] S.C.Chiou, “Colored and Timed Petri Net-based operation sequence control logic modeling of physical vapor deposition (PVD) equipment,” Institute of Industrial Engineering College of Engineering Nation Taiwan University, Master Thesis. [4] R. S. Srinivasan, 'Modeling and Performance Analysis of Cluster Tools Using Petri Nets,' IEEE Trans. on Semi. Mfg., 11:394-403, 1998 [5] A.N. Swe, A.K. Gupta, A.I. Sivakumar, P. Lendermann, 'Cycle Time Reduction at Cluster Tool in Semiconductor 晶圓 Fabrication,' Electr. Packaging Tech. Conf. EPTC '06. 8th, SG pp. 671-677 Dec., 2006 [6] CPN tools [Online]. Available: http://wiki.daimi.au.dk /cpntools [7] Dummler, M. 2004. “Modeling and Optimization of Cluster Tools in Semiconductor Manufacturing.” PhD thesis, Department of Computer Science. University of Wurzburg, Germany [8] N. Wu and M. C. Zhou, “Schedulability and scheduling of dual-arm cluster tools with residency time constraints based on Petri net,” in Proc. IEEE Conf. Autom. Sci. Eng.,Shanghai, China, 2006, pp. 85–90 [9] C.-H. Hu, D.-Y. Liao, S.-C. Chang, “Sequencing and performance analysis system design for semiconductor manufacturing cluster tools: a PVD example,” submitted to AOTOMATION 2000, Sept., 1999 [10] Applied EnduraR 2 [Online]. Available: http://www.appliedmaterials.com/products/assets/conductor_deposition/31_End2_noKPI.pdf [11] “Centura 5200 Systems Platform Functional Description,” Applied material Corporation, Taiwan, Oct. 1997 [12] E. Keller, J. Bukhman, S. Gonzales, C. Magnella, J. Nulman, R. Mosely, H. Grunes, and A. Tepman, “Manufacturing Evaluation of an Endura 5500 PVD Multichamber System,” Solid state technology, vol. 35, no2, pp. 71-74, Feb. 1992 [13] J.L. Peterson, “Petri net theory and the modeling of systems,” Prentice Hall, Englewood Cliffs, 1981 [14] W. M. Zuberek, “Timed Petri net models of cluster tools,” Proc. IEEE Int. Conf. on Systems, Man, and Cybernetics (SMC'2000), 8-11 October 2000, Nashville, TN, Vol. 4, pp. 3063-3068. 2000 [15] P.M. Hsu, J.L. Chen, Joey Chang, S.C. Chiou, S. C. Chang, L.L. Sun, Peter B. Luh, “Design of Standard Modeling Process for Tool Sequencing Optimization under Given Robot Control Logics: A PVD Case,” Semiconductor Manufacturing (ISSM), 2010 International Symposium, Tokyo, Oct. 2010 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/36406 | - |
| dc.description.abstract | 半導體晶圓廠購置設備的花費約佔建廠總額的七成以上,生產設備作業運用的效能因此攸關晶圓廠投資收益。本論文研究針對晶圓廠製程設備,以爐管(Furnace)和物理氣象沉積(PVD)兩類為案例,探討如何協助設備工程師有效建構設備機台作業順序模型、並進行效能分析與驗證,以做為設備作業順序最佳化之用。研究主要的挑戰在提供一套系統方法與工具環境,讓一般設備工程師有模組(module)及導引規則(guidelines)可容易地重覆運用,來(i) 描述半導體設備作業流程與觀察到的內部/外部控制邏輯, (ii)快速進行模擬驗證、追蹤修改所描述的模型,以及(iii)轉換所建模型為設備機台作業順序最佳化的限制條件(constraints)。
對於上述三項挑戰,本論文分別研發設計了解決方案:(1) 利用邱顯強2010年碩士論文以PⅤD機台為案例所研發的模組化斐式網建模方法、設備控制邏輯以語意式描述與功能性拆解的方法、及所建出的模型模組,推展至 Furnace內部及外部控制邏輯、出入口傳輸邏輯等(2) 利用CPN tools斐式網模擬軟體分析效能並比對各項效能及作業模式的差異找出了模型是否需要調整或修改,(3)以及藉由斐式網模型轉換為最佳化求解所需限制式模型的說明。 在模型驗證的部分,本文利用線上所使用的機台配置與規則建構其對應的斐式網模型,並且以實際的使用狀況比對模型模擬得到的結果,驗證模型之真實性以及有效性;在行為的驗證上,採用了PVD的推式控制邏輯,以及Furnace的外部邏輯。以晶圓產出之間隔時間以及資源占用時間作為主要驗證的指標並說明如何比對其操作上的差異以快速追蹤模型不足之處。 驗證後的斐式網模型可經由系統化的最佳化限制式模型轉換。藉由定義最佳化之目標函式,便可利用套裝軟體求解。得到的結果將可提供業者量化的效能指標,諸如晶圓產出間隔時間、使用率、製程完成時間等,及發現可能的作業順序控制邏輯選用或設計所能帶來的改善空間,進而提升半導體設備整體作業生產效能。 | zh_TW |
| dc.description.abstract | In the construction of a semiconductor fab., the cost of equipment is above 70% of the total cost. Therefore the production equipment performance is directly reflexes in the invest reward in the industry. This paper is focus on 'semiconductor fab.', using the case of Furnace Tools and PVD Cluster tools as example to discuss how to assist equipment engineer to efficiently construct the tool sequence model and validate the significance of model. In the end, the model should be able to provide the optimal or near optimal sequence.
Designing a systematic guideline for tool sequence modeling method, that a general equipment engineers can construct reusable, modules to fast up the tool sequence modeling process. For this propose, the key challenges is (i) to describe the observed internal/external control logic and (ii) to validate, and quick localize error and revise the just constructed module or complete model and (iii) to convert the constructed model into the constraint form for optimization package usage. In respect of these challenges, in this paper suggested following methods, (1) Adopt the method designed by S.C.Chiou Petri Net PVD Cluster tool robot control logic modeling, which consists in the syntax description and function decomposition methodology. This method helps engineers efficiently construct modules; in this paper we enriched this method to specific furnace such as internal/external control logic, Queue time consideration. (2) Applying the software CPN tools to simulate the constructed models, by token flow and variable design to obtain the necessary information for behavior and performance analysis, as Petri Net has a graphic structure; the error can be located easily. (3) Using the method cooperated designed by Inotera, University of Connecticut and National Taiwan University to module and systematically convert the math form PN model into its constraint form. In this paper, a PVD real fabric operation data is used to validate the constructed model, the error is within 1 sigma (about 2%), and the optimized sequence has the same behavior and performance as real data, it shows that this method can result an optimal sequence of fab. tools, and the real operation sequence is near optimal. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T07:59:43Z (GMT). No. of bitstreams: 1 ntu-100-R98921080-1.pdf: 2013239 bytes, checksum: d01d7ec5f6c340315334cc519300d8cb (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | 中文摘要 i
Abstract iii 目錄 v 圖目錄 vii 表目錄 viii 第一章 半導體設備作業順序簡介 1 1.1 半導體機台特性簡介 3 1.2 文獻探討 – 現有的半導體傳輸程序建模方法 5 1.3 研究範疇 7 1.4 論文架構 9 第二章 PVD 與 Furnace半導體設備作業順序簡介 10 2.1 PVD設備模組簡介 12 2.2 PVD控制邏輯模組 17 2.3 Furnace設備模組簡介 21 2.4 Furnace控制邏輯模組 25 2.5 PVD 以及Furnace作業流程最佳化之需求 28 2.6 研究挑戰 29 第三章 半導體設備斐式網建模 30 3.1 斐式網簡介 31 3.1.1 彩色時間斐式網 33 3.1.2 現有斐式網建模 34 3.2 利用觀察的控制邏輯建模導引 36 3.2.1 語法式控制邏輯描述 36 3.2.2 控制邏輯功能性拆解 38 3.2.3 資源模組 42 3.2.4 手臂控制邏輯模組 45 3.2.5 晶圓生產流程 50 第四章 彩色時間斐式網模型驗證 54 4.1 驗證的理論與基礎 55 4.2 模擬執行與效能指標取得 56 4.3 驗證結果 61 第五章 機台作業程序最佳化之應用 65 5.1 利用PN model建立流程最佳化的限制式數學模型 66 5.2 機台作業結果及模擬評估 72 第六章 結論與未來研究方向 74 參考文獻 77 | |
| dc.language.iso | zh-TW | |
| dc.subject | 作業順序最佳化 | zh_TW |
| dc.subject | 斐式網 | zh_TW |
| dc.subject | 半導體設備建模 | zh_TW |
| dc.subject | Sequence optimization | en |
| dc.subject | Petri Net | en |
| dc.subject | Semiconductor tool modeling | en |
| dc.title | 半導體設備作業順序最佳化的斐式網建模:以爐管及物理氣象沉積為例 | zh_TW |
| dc.title | Semiconductor Tool Petri Net Modeling for Sequence Optimization: Furnace and PVD Cluster Tool Cases | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 張展裕(Joey Chang),許丕敏(Pi-Ming Hsu) | |
| dc.subject.keyword | 斐式網,半導體設備建模,作業順序最佳化, | zh_TW |
| dc.subject.keyword | Petri Net,Semiconductor tool modeling,Sequence optimization, | en |
| dc.relation.page | 78 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2011-08-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位: | 電機工程學系 | |
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