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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模(Chien-Mo Li) | |
| dc.contributor.author | Jhih-Kai You | en |
| dc.contributor.author | 游智凱 | zh_TW |
| dc.date.accessioned | 2021-06-13T07:48:36Z | - |
| dc.date.available | 2005-07-30 | |
| dc.date.copyright | 2005-07-30 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-07-26 | |
| dc.identifier.citation | [Abramovici 80] M. Abramovici and M. A. Breuer, “Multiple Fault Diagnosis in Combinational Circuits Based on Effect-Cause Analysis,“ IEEE Trans. Comput., vol. 29, pp. 451-460, June 1980.
[Abramovici 95] M. Abramovici, M. A. Breuer, and A. D. Fridman, Digital Systems Testing and Testability Design, IEEE Press, Piscataway, N.J., 1995, ch. 12. [Bushnell 00] M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-signal VLSI Circuits, p. 226, Boston: Kluwer Academic Publishers, 2000. [Edirisooriya 95] S. Edirisooriya, and G. Edirisooriya, “Diagnosis of Scan Path Failures,” Proc. IEEE VLSI Test Symp., pp. 250-255, 1995. [Girard 92] P. Girard, C. Landrault, and S. Pravossoudovitch, “A Novel Approach to Delay-Fault Diagnosis,” Proc. Design Autom. Conf., pp. 357-360, 1992. [Guo 01] R. Guo, and S. Venkataranman, “A Technique for Fault Diagnosis of Defects in Scan Chains,” Proc. IEEE Int’l Test Conf., pp. 268-277, 2001. [Guo 02] R. Guo, and S. Venkataranman , “A New Technique for Scan Chain Failure Diagnosis,” Proc. Int’l Symp. Testing and Failure Analysis, pp. 723-732, 2002. [High 98] P. High, D. Vallett, A. Patel and et. al., “Failure Analysis of Timing and IDDq Failures from the SEMATECH Test Methods Experiment,“ Proc. IEEE Int’l. Test Conf., pp.43-52 , 1998. [Hirase 99] J. Hirase, N. Shindou, and K. Akahori, “Scan Chain Diagnosis Using IDDQ Current Measurement,” Proc. Asian Test Symp. pp. 153-157, 1999. [Huang 03] Y. Huang, W.-T. Cheng, S. M. Reddy, C.-J. Hsieh, and Y.-T. Hung, “Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault,” Proc. IEEE Int’l Test Conf., pp. 319-327, 2003. [Iyer 96] M. A. Iyer, and M. Abramovici, “FIRE: A Fault-Independent Combinational Redundancy Identification Algorithm,” IEEE Trans. VLSI Syst., vol. 4, no. 2, pp. 295-301, June 1996. [Jha 03] N. K. Jha and S. Gupta, Testing of Digital Systems, Cambridge University Press, 2003, ch. 10. [Kautz 68] W. H. Kautz, “Fault Testing and Diagnosis in Combinational Digital Circuits,” IEEE Trans. Comput., vol. 17, pp. 352-366, Apr. 1968. [Koren 96] I. Koren, Z. Koren, and C. H. Stapper,”A statistical study of defect maps of large area VLSI IC's,” IEEE Trans. VLSI Syst., vol. 2, no. 2, pp. 249-56, 1996. [Kundo 94] S. Kundu, “Diagnosis Scan Chain Faults,” IEEE Trans. VLSI Syst., pp. 512-516, 1994. [Li 02] J. C.-M. Li and E. J. McCluskey, “Diagnosis for Sequence Dependent Chips,” Proc. IEEE VLSI Test Symp., pp. 187-192, 2002. [Li 05] J. C.-M. Li, “Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns”, IEICE Tran . on Electronics, 2005 [Li 05] J. C.-M. Li, “Diagnosis of Single Stuck-at faults and Multiple Timing Faults in Scan Chains”, IEEE Trans. on VLSI Sys. 2005 [Makar 95] S. Makar and E. J. McCluskey, “Functional Tests for Scan Chain Lat ches, “Proc. IEEE Int’l. Test Conf., pp. 606-615, 1995. [McCluskey 00] E. J. McCluskey and C. W. Tseng, 'Stuck-Fault vs. Actual Defects,' Proc. IEEE Int’l Test Conf., pp. 3356-343, 2000. [Narayanan 97] S. Narayanan and A. Das, “An Efficient Scheme to Diagnose Scan Chains,” Proc. Int’l Test Conf., pp.704-713, 1997. [Rajski 88] H. Cox and J. Rajski, “A Method of Fault Analysis for Test Generation and Fault Diagnosis,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 813-833, July 1988. [Reddy 00] S. M. Reddy, I. Pomeranz, S. Kajihara, A. Murakami, S. Takeoka, and M. Ohta, “On Validating Data Hold Times for Flip-flops in Sequential Circuits,” Proc. IEEE Int’l. Test Conf., pp.317-325, 2000. [Richman 85] J. Richman and K. R. Bowden, “The Modern Fault Dictionary,” Proc. IEEE Int’l Test Conf., pp. 696-702, 1985. [Schafer 92] J. Schafer, F. Policastri and R Mcnulty, “Partner SRLs for Improved Shift Register Diagnostics,” Proc. IEEE VLSI Test Symp., pp. 198-201, 1992. [Stanley 01] K. Stanley, “High-Accuracy Flush-and-scan Software Diagnostic,” IEEE Des. Test. Comput., pp. 56-62, Nov-Dec, 2001. [Synopsys 03] Synopsys, TetraMAX ATGP User Guid, V-2003.12, Dec. 2003, ch. 18. [Mentor 03] Mentor Graphics, Scan and ATPG Process Guide, V 8.2003_4, 2003, ch8. [Venkataraman 01] S. Venkataraman and S. B. Drummonds, “Poriot: Applications of a Logic Fault Diagnosis Tool,” IEEE Des. Test. Comput., pp. 19-29, Jan-Feb, 2001. [Wu 98] Y. Wu, “Diagnosis of Scan Chain Failures,” Int’l Symp. On Defect and Fault Tolerance in VLSI systems, pp. 217-222, 1998. [Waicukauski 87] J. A. Waicukauski, E. Lindbloom, B. K. Rosen, and V. S. Iyenggar, “Transition Fault Simulation,” IEEE Des. Test. Comput., vol. 4, pp. 32-38, 1987. [Waicukauski 89] J. A. Waicukauski and E. Lindbloom, “Failure Diagnosis of Structured VLSI,” IEEE Des. Test. Comput., vol.6. pp. 49-60, Aug. 1989. [Williams 96] T. Williams, R.H. Dennard, R. Kapur, M.R. Mercer, and W. Maly, “IDDQ Test: Sensitivity Analysis of Scaling,” Proc. IEEE Int’l Test Conf., pp. 786-792, 1996. [Yo 04] C. -K. Yo and C. -M. Li, “Diagnosis of Scan Chains with Multiple Timing Faults Using Single Excitation Patterns,” VLSI/CAD Symposium, pp.94, 2004 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/35946 | - |
| dc.description.abstract | 為改善掃描鏈之單一黏著性錯誤之診斷解析度，本研究提出掃描鏈之分割與重排技術。掃描鏈分割技術即將單一條掃描鏈分割為兩條以上。掃描鏈分割技術可藉由解決可控制性問題及可觀察性問題來改善診斷解析度。掃描鏈重排技術即改變掃描正反器之排列順序。掃描鏈重排技術可藉由打斷連續之不可觀察的掃描正反器來改善診斷解析度。為降低掃描鏈重排所造成之繞線增加，本研究亦支援以叢集為基礎之重排技術。實驗結果證明所提出之技術可有效改善診斷解析度。 | zh_TW |
| dc.description.abstract | Scan chain partition and reordering techniques are proposed to improve the diagnosis resolutions of scan chain single stuck-at faults. Scan chain partition separates a scan into two or more chains. Scan chain partition improves diagnosis resolutions by solving controllability problems and observability problems. Scan chain reordering changes the order of scan cells. Scan chain reordering improves diagnosis resolutions by breaking the continuous unobservable scan cells. Cluster-based reordering is supported to improve the scan chain wiring overhead. Experimental results shows the proposed techniques are effective. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T07:48:36Z (GMT). No. of bitstreams: 1 ntu-94-R92943066-1.pdf: 438554 bytes, checksum: c72fcbdf8ebaeb83e8fffd850b0627c1 (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | 誌謝 I
摘要 III Abstract IV Table of Contents V List of Figures VII List of Tables VIII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Contributions 2 1.3 Organization 3 Chapter 2 Background 4 2.1 Past Research in Scan Chain Diagnosis 4 2.2 Scan Chain Diagnosis Using Single Excitation Patterns 6 2.2.1 Scan Chain Stuck-at Fault 6 2.2.2 Single Excitation (SE) Pattern 8 2.2.3 Diagnosis Flow 9 2.2.4 Combinational Diagnosis Procedure (CDP) 10 2.2.5 C-ADPG Method 11 2.2.6 Diagnosis Resolution (DR) 13 Chapter 3 Proposed Technique 15 3.1 Scan Chain Reordering 15 3.1.1 Reordering without clusters 15 3.1.2 Reordering with clusters 22 3.2 Scan Chain Partition 23 3.3 Partition Plus Reordering 31 Chapter 4 Experimental Results 32 4.1 Diagnosis Resolutions 32 4.2 Scan Chain Wiring Overhead 40 Chapter 5 Discussion and Future Work 46 5.1 Discussion 46 5.2 Future Work 48 Chapter 6 Summary 49 References 50 | |
| dc.language.iso | en | |
| dc.subject | 輸出響應矩陣 | zh_TW |
| dc.subject | 掃描鏈 | zh_TW |
| dc.subject | 分割 | zh_TW |
| dc.subject | 重排 | zh_TW |
| dc.subject | 叢集 | zh_TW |
| dc.subject | 診斷解析度 | zh_TW |
| dc.subject | 平均診斷解析度 | zh_TW |
| dc.subject | 最差診斷解析度 | zh_TW |
| dc.subject | 輸入測試方塊矩陣 | zh_TW |
| dc.subject | average DR | en |
| dc.subject | worst DR | en |
| dc.subject | scan chain | en |
| dc.subject | partition | en |
| dc.subject | reordering | en |
| dc.subject | cluster | en |
| dc.subject | diagnosis resolution(DR) | en |
| dc.subject | ORM | en |
| dc.subject | ITCM | en |
| dc.title | 掃描鏈分割與重排之掃描鏈黏著性錯誤診斷技術 | zh_TW |
| dc.title | A Scan Chain Partition and Reordering Technique for Scan Chain Stuck-At Fault Diagnosis | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃錫瑜(Shi-Yu Huang),呂學坤(Shyue-Kung Lu) | |
| dc.subject.keyword | 掃描鏈,分割,重排,叢集,診斷解析度,平均診斷解析度,最差診斷解析度,輸入測試方塊矩陣,輸出響應矩陣, | zh_TW |
| dc.subject.keyword | scan chain,partition,reordering,cluster,diagnosis resolution(DR),average DR,worst DR,ITCM,ORM, | en |
| dc.relation.page | 53 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2005-07-26 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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