單晶片電視調諧器其相位雜訊之經濟有效測試方法

Abstract

由於電視調諧器須要處理大量的電視頻道，故其相位雜訊之測試十分的耗時且昂貴。本論文針對複雜的單晶片電視調諧器之相位雜訊提出一階層式的模擬方法。根據此模擬方式所得到的結果，進而提出一經濟有效的相位雜訊測試方法以節省量產測試的時間。此測試方法能決定出最有效的頻道及頻率進行測試，以減少相位雜訊的測試次數。對部分商用電視調諧器的電路樣本進行實驗，其結果顯示本論文所提出的方法能使測試時間降為約原來的十分之一，並且不會發生測試逃脫。

Phase noise testing for TV tuners is time consuming and expensive because of the great number of TV channels. This thesis presents a hierarchical simulation method for a complicated single chip TV tuner. Based on the simulation results, an effective and economic test method is proposed to save the test application time. This method determines the most effective channels and frequencies to test so the number of phase noise measurements is reduced. Experimental results on commercial chips show that our proposed method reduces the test time by ten times without test escapes.