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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 闕志達(Tzi-Dar Chiueh) | |
dc.contributor.author | Keng-Hsien Lin | en |
dc.contributor.author | 林耕賢 | zh_TW |
dc.date.accessioned | 2021-06-13T06:50:48Z | - |
dc.date.available | 2005-07-30 | |
dc.date.copyright | 2005-07-30 | |
dc.date.issued | 2005 | |
dc.date.submitted | 2005-07-28 | |
dc.identifier.citation | [1] Y.J. Chen, “Baseband Transceiver Design for the DVB-Terrestrial Standard,” Master Thesis, Graduate of Institute Electronics Engineering, National Taiwan University, Taipei, Taiwan, Jun. 2004.
[2] http://www.dtvc.org.tw/DTVC/ [3] “Digital Video Broadcasting (DVB); Framing Structure, Channel Coding and Modulation for Digital Terrestrial Television,” ETSI EN 300 744 v1.5.1, Nov. 2004. [4] “Digital Video Broadcasting (DVB); Implementation Guidelines for DVB Terrestrial Services; Transmission Aspects,” ETSI TR 101 190 v1.2.1, Nov. 2004. [5] P. Y. Tsai, H. Y. Kang, and T. D. Chiueh, “Joint Weighted Least Squares Estimation of Frequency and Timing Offset for OFDM Systems over Fading Channels,” in Proc. of 2003 IEEE VTC, Apr. 2003. [6] Z. Wang and G. B. Giannakis, “Wireless Multicarrier Communications: Where Fourier Meets Shannon,” IEEE Signal Processing Magazine, May. 2000. [7] S. H. Chen, W. H. He, H. S. Chen, and Y. M. Lee, “Mode Detection, Synchronization, and Channel Estimation for DVB-T OFDM Receiver,” Global Telecommunications Conference, Dec. 2003. [8] J. S. Wu, M. L. Liou, H. P. Ma, and T. D. Chiueh, “A 2.6-V, 44-MHz All-Digital QPSK Direct-Sequence Spread Spectrum Transceiver IC,” IEEE JSSC, Oct. 1997 [9] L. Erup, F. M. Gardner, and R. A. Harris, “Interpolation in Digital Modems-Part II: Implementation and Performance,” IEEE Transaction on Communications, Jun. 1993. [10] S. He and M. Torkelson, “A New Approach to Pipeline FFT Processor,” in Proc. of IPPS’96, Apr. 1996. [11] L. Jia, Y. Gao, J. Isoaho, and Tenhunen, “A New VLSI-Oriented FFT Algorithm and Implementation,” in Proc. of ASIC Conference, Sep. 1998. [12] Y.T. Lin, “Design and Implementation of a Variable-Length FFT Processor for OFDM Systems,” Master Thesis, Graduate of Institute Electrical Engineering, National Taiwan University, Taipei, Taiwan, Jun. 2001. [13] J. G. Proakis, Digital Communications, 4th Ed., McGraw-Hill, 2001. [14] P. Y. Tsai and T. D. Chiueh, “Frequency-Domain Interpolation-Based Channel Estimation in Pilot-Aided OFDM Systems,” IEEE VTC, May 2004. [15] F. Tosato and P. Bisaglia, “Simplified Soft-Output Demapper for Binary Interleaved COFDM with Application to HIPERLAN/2,” IEEE ICC, Apr. 2002. [16] R. Andraka, “A Survey of CORDIC Algorithms for FPGA based Computers,” 1998. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/35391 | - |
dc.description.abstract | 本論文依據歐規數位電視地面廣播(DVB-T)標準的傳送機架構和系統規格,提出基頻等效通道模型,並設計及實作一基頻接收機。基頻等效通道模型包括多路徑衰減通道(Multipath Fading Channel)、加成性白色高斯雜訊(Additive White Gaussian Noise,AWGN)、載波頻率漂移(Carrier Frequency Offset,CFO)、取樣時脈漂移(Sampling Frequency Offset,SCO)和相位雜訊(Phase Noise)等效應。而因為DVB-T在系統規格上,可以選擇2種快速傅立葉轉換(Fast Fourier Transform,FFT)大小和4種保護區間比例(Guard-Interval Ratio,GR)大小,所以在接收機的架構演算法設計上,一開始就必須偵測傳送機所使用的FFT模式及GR模式。本論文設計提出了一兩階段模式偵測演算法來實現接收機一開始所需的模式偵測功能,並結合符元時間偵測、載波頻率漂移及取樣時脈漂移之擷取、補償和追蹤、2k-8k FFT處理器、相位調整、通道估測與補償、軟性輸出解映射器(Soft-Out De-Mapper)及軟性輸入維特比解碼器(Soft-In Viterbi Decoder)等演算法來實現整個DVB-T基頻接收機系統。在硬體電路方面,本論文也提出使用輸出訊噪比(Output SNR)取代位元錯誤率(Bit Error Rate,BER)來做為取最佳位元數的指標,並在演算法可容忍些微誤差下,為了節省硬體,提出了分段線性近似的演算法。經過系統效能模擬與全系統RTL Verilog的實作驗證,說明了本論文所提出的DVB-T基頻接收機是可以良好工作的。 | zh_TW |
dc.description.abstract | This thesis proposes a baseband receiver and a baseband equivalent channel model according to the transmitter and system specification of Euporean DVB-T standard. The baseband equivalent channel model includes effects of multipath fading channel, Additive White Gaussian Noise (AWGN), Carrier Frequency Offset (CFO), Sampling Frequency Offset (SCO), and phase noise. DVB-T system has two choices in Fast Fourier Transform (FFT) size and four choices in Guard-Interval Ratio (GR) size, so a DVB-T reciever should detect FFT mode and GR mode used in the transmitter in the beginning. This thesis proposes a two-stage mode detection algorithm to perform the function, and combines algorithms of symbol timing detection, CFO acquisition, compensation, and tracking as well as SCO, 2k-8k FFT processor, phase modification, channel estimation and compensation, soft-out demapper, and soft-in Viterbi decoder to implement the whole system of DVB-T receiver. In hardware circuit design, this thesis also proposes to use output SNR instead of Bit Error Rate (BER) as the metric of optimum wordlength and use piecewise linear approximation algorithm to save hardware cost with tolerable approximation error. Through system performance simulation and verification of whole system RTL Verilog, the proposed DVB-T baseband receiver is proven to work well. | en |
dc.description.provenance | Made available in DSpace on 2021-06-13T06:50:48Z (GMT). No. of bitstreams: 1 ntu-94-R92943078-1.pdf: 5977565 bytes, checksum: 218f24bcd6bbb9c526f1fd51849b070e (MD5) Previous issue date: 2005 | en |
dc.description.tableofcontents | 目錄 i
圖示列表 v 表格列表 xi 第一章 緒論 1 1.1 研究動機 1 1.2 歐規數位電視廣播(DVB)之介紹 2 1.2.1 DVB-T、DVB-C、DVB-S、DVB-H之比較 3 1.3 現行各數位電視地面廣播標準之比較 4 1.4 台灣無線數位電視之發展 5 1.5 論文組織介紹 6 第二章 歐規數位電視地面廣播(DVB-T)之規格 9 2.1 正交分頻多工(OFDM)調變介紹 9 2.1.1 OFDM之數學模型 11 2.1.2 Guard Interval and Cyclic Prefix 14 2.1.3 OFDM系統之優缺點 16 2.2 DVB-T系統規格參數簡介 18 2.2.1 階層調變資訊(Hierarchy Information) 20 2.2.2 訊框格式(Frame Format) 21 2.3 傳送端(Transmitter)系統架構 25 2.3.1 方塊圖(Block Diagram) 25 2.3.2 內編碼器(Inner Coder) 27 2.3.3 內交錯器(Inner Interleaver) 29 2.3.4 映射器(Mapper) 29 2.3.5 訊框建構(Frame Adaptation) 31 2.4 本章總結 32 第三章 基頻通道(Baseband Channel)之模擬 35 3.1 方塊圖(Block Diagram) 35 3.2 通道模型(Channel Model) 36 3.2.1 F1通道模型 36 3.2.2 P1通道模型 38 3.3 加成性白色高斯雜訊(AWGN) 41 3.4 載波頻率漂移(Carrier Frequency Offset) 42 3.5 取樣時脈漂移(Sampling Clock Offset) 43 3.6 相位雜訊(Phase Noise) 44 3.7 本章總結 45 第四章 接收端(Receiver)系統之演算法及架構設計 47 4.1 方塊圖(Block Diagram) 47 4.2 模式偵測(Mode Detection) 48 4.1.1 FFT Mode Detection 49 4.1.2 GR Mode Detection 51 4.3 符元時間偵測(Symbol Timing Detection) 53 4.4 載波頻率漂移之擷取(CFO Acquisition) 56 4.4.1 分數載波頻率漂移之擷取(Fractional CFO Acquisition) 57 4.4.2 整數載波頻率漂移之擷取(Integer CFO Acquisition) 58 4.5 取樣時脈漂移之擷取(SCO Acquisition) 59 4.6 載波頻率漂移與取樣時脈漂移之追蹤(CFO and SCO Tracking) 60 4.7 載波頻率漂移與取樣時脈漂移之補償(CFO and SCO Compensation) 62 4.7.1 載波頻率漂移之補償(CFO Compensation) 62 4.7.2 取樣時脈漂移之補償(SCO Compensation) 63 4.8 2k-8k快速傅立葉處理器(2k-8k FFT Processor) 64 4.9 相位調整(Phase Modification) 65 4.10 通道估測與補償(Channel Estimation and Compensation) 67 4.11 解映射器(De-Mapper) 69 4.12 外接收機(Outer Receiver) 74 4.13 系統模擬(System Simulation) 75 4.14 本章總結 82 第五章 接收端系統之定點數模擬及電路設計 83 5.1 方塊圖(Block Diagram) 83 5.2 定點數模擬(Fixed-Point Simulation) 84 5.3 數位座標旋轉器(CORDIC)之演算法 92 5.4 分段線性近似(Piecewise Linear Approximation)之演算法 95 5.5 電路設計(Circuit Design) 99 5.6 本章總結 119 第六章 硬體實作及模擬驗證結果 121 6.1 RTL Verilog模擬驗證結果 121 6.2 系統BER效能比較 128 6.3 本章總結 131 第七章 結論及展望 137 參考資料 139 | |
dc.language.iso | zh-TW | |
dc.title | 歐規數位電視地面廣播基頻接收機之設計 | zh_TW |
dc.title | Design of a Baseband Receiver for DVB-T Standard | en |
dc.type | Thesis | |
dc.date.schoolyear | 93-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 趙啟超(Chi-Chao Chao),黃元豪(Yuan-Hao Huang),馬席彬(Hsi-Pin Ma) | |
dc.subject.keyword | 數位電視,基頻接收機,正交分頻多工,基頻通道,定點數,電路設計, | zh_TW |
dc.subject.keyword | Digital TV,Baseband Receiver,OFDM,Baseband Channel,Fixed-Point,Circuit Design, | en |
dc.relation.page | 140 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2005-07-28 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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