可變動高速奇偶校驗編碼之解碼器結構設計

Abstract

Low-density parity check (LDPC) codes have been shown that it is a strong competitor of Turbo codes. LDPC codes offer excellent coding gain and provide elegant low computation complexity when comparing with Turbo codes. The complex routing nature of LDPC decoder and low hardware utilization efficiency are the major implementation challenges. In this thesis we design an elitist scheduling algorithm called “Jump-Reset Scheduling Algorithm” to boost hardware utilization efficiency (HUE) of low-density parity check (LDPC) decoder. This algorithm supports a scalable pipeline decoding architecture. The architecture is a semi-parallel decoder with a scalability factor. It offers flexible tradeoff between hardware cost and throughput. A high HUE and scalable decoding architecture is implemented. This architecture is decoding algorithm independent from decoding algorithm. Sum-product algorithm and min-sum algorithm can be applied to this architecture. We use a modified min-sum algorithm as decoding algorithm in this decoder. This algorithm only contains additions and comparisons. There are no large LUTs for non-linear function in bit-to-check functional units. The modified min-sum algorithm can improve BER performance extremely close to sum-product algorithm. Word length effect on BER performance is analyzed. This thesis presents a scalable pipelined architecture with single size of memory and extremely high hardware utilization efficiency. This architecture can offer double throughput of traditional architecture without increasing memory requirement.