請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/35233完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳中平(Charlie Chung-Ping Chen) | |
| dc.contributor.author | Ming-Zhang Kuo | en |
| dc.contributor.author | 郭明璋 | zh_TW |
| dc.date.accessioned | 2021-06-13T06:44:55Z | - |
| dc.date.available | 2007-08-01 | |
| dc.date.copyright | 2005-08-01 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-07-29 | |
| dc.identifier.citation | [1] G.K.Konstadinidis et al. The implementation of a Third-Generation 1.1-GHz
64-bit Microprocessor. IEEE journal of Solid-State Circuits (Nov. 2002), 1461-1469. [2] J.Montanaro, R.T Witek, K, Anne, A.J. Black, E.M. Cooper, D.W. Dobberpuhl, P.M.Donahue, J.Eno, A.Farell, G.W.Hoeppner, D.Kruckemyer, T.H.Lee, P.Lin, L.Madden, D.Murray, M.Pearce, S.Santhanam, K.J.Snyder, R.Stephany, Thier. A 160 MHz 32 b 0.5 W CMOS RISC microprocessor. In IEEE Solid-State Circuits Conference (Feb 1996), pp. 214-215. [3] S.D. Naffziger, G.Colon-Bonet, T.Fischer, R.Riedlinger, T.J.Sullivan, T.Grutkowski. The implementation of the Itanium 2 microprocessor. IEEE Journal of Solid-State Circuits (Nov. 2002),1448-1460. [4] W.J.Bowhill, R.L.Allmon, S.L.Bell, E.M.Cooper, D.R. Donchin, J.H. Edmondson, T.C.Fischer, P.E.Gronowski, A.K.Jain, P.L.Kroesen, B.J.Loughlin, R.P.Preston, P.I.Rubinfeld, M.J.Smith, S.C.Thierauf, G.M.Wolrich. A 300MHz 64b quad-issue CMOS RISC microprocessor. In IEEE Solid-State Circuits Conference (Feb. 1995), pp.182-183. [5] K.Itoh, “VLSI Memory Chip Design”,Baifukan, Tokyo, 1994. [6] Itoh, Kiyoo, Sasaki, Katsuro, and Nakagome, Yoshinobu, “Trends in Low-Power RAM Circuit Technologies”, Proceedings of the IEEE, vol. 83, pp. 524-543, april 1995. [7] Dally, William J. and Poulton, John W., Digital Systems Engineering, University Press, Cambridge, 1998. [8] Keeth, Brent and Baker, Jacob R., DRAM Circuit Design - A Tutorial, IEEE Press, New York, 2001. [9] Tegze P. Haraszti. CMOS Memory Circuits. Kluwer Academic Publishers, 2000. [10] E. Seevinck Sr., F.J. List, and J. Lohstroh. Static-noise margin analysis of MOS SRAM cells. IEEE Journal of Solid-state Circuits, 22:748-754, October 1987. [11] Azeez J. Bhavnagarwala, Xinghai Tang, and James D. Meindl. The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE Journal of solid-state Circuits, 36:658-665, April 2001 [12] Rabaey, Jan M., Digital Integrated Circuits - A Design Perspective, Prentice Hall, Upper Saddle River, New Jersey, 1996. [13] Bharadwaj S. Amrutur and Mark A. Horowitz,“A replica technique for wordline and sense control in Low-Power SRAM’s” IEEE Journal of Solid-State Circuits, Vol. 33, NO. 8, August 1998 [14] E. Sccvinck, P.J. van Beers, and H.Ontrop, “Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM’s,”IEEE Journal of solid-State Circuits Vol1.26 No.4 pp.525-536 April 1991 [15] B. Razavi,“Design of Analog CMOS Integrated Circuits,” Mcgraw-Hill international Edition, 2001. [16] V.Kristovski and Y.L.Pogrbeny,“New Sense Amplifier for Small-Swing CMOS Logic Circuits,” IEEE Trans, On Circuit and Systems, vol. 47, p.p 573-576, June, 2000 [17] J.R. Cavaliere, “Sense Amplifier,” United States Patent 3,879,632, Apr. 18, 1973. [18] D. C. Galbraith, “Dynamic Sense Amplifier for CMOS Static RAM,” United States Patent 4,843,264, June, 1989. [19] Singh, Shobha, Azmi, Shamsi, Agrawal, Nutan, Phani, Penaka, and Rout, Ansuman, “Architecture and Design of a High Performance SRAM for SOC Design”, Proceedings of the 15th International Conference on VLSI Design, pp. 447-451, 2002. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/35233 | - |
| dc.description.abstract | 這篇論文的主題是描述如何實現一個四千位元的靜態隨機存取記憶體電路。為了要達到可以在低工作電壓下正確地讀取資料，本文提出了一種改良式電流栓鎖感測放大器電路。這篇論文總共分為五個章節，其中第一章及第五章為導論及結論，在第二章裡，將會介紹整體靜態隨機存取記憶體的電路架構，同時也將介紹各個基本電路及其設計考量。
在第三章裡我們將分析感測放大器。 由於輸入阻抗的差異，感測放大器在時間延遲的表現上有很大的差別。同時也將介紹幾種常用的感測放大器並分析其優缺點以及對常用的電流栓鎖感測放大器作些微的修改使其適用於低工作電壓。 第四章裡詳述了電路實作，我們使用0.18um標準互補式金氧半製程實現一個四千位元的靜態隨機存取記憶體電路。我們所實現的靜態隨機存取記憶體電路讀取延遲時間為2.0557nS。晶片的主體佔了1.056002 ╳ 1.090342 mm2，當電路工作在250MHz的情況下，整個電路消耗了15.658毫瓦。 | zh_TW |
| dc.description.abstract | Abstract
This thesis describes the implementation of a 4Kb static random access memory circuit. In order to correctly perform a read operation at low voltage, the current latched sense amplifier is improved. This thesis is divided into five chapters. The first chapter is the introduction. In the chapter 2, the architecture and the design considerations of SRAM are presented. In chapter 3, we describe the sense amplifiers in detail. The difference of the input resistance makes the delay differ a lot in sensing time. Chapter 4 presents the circuit implementation. A 4Kb SRAM is implemented with a standard 0.18um CMOS process. The access time of SRAM is 2.0557ns. The core circuit of the chip occupies 1.056002 ╳ 1.090342 mm2 and it consumes 15.658mW when working at 250MHz. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T06:44:55Z (GMT). No. of bitstreams: 1 ntu-94-R92943065-1.pdf: 2729770 bytes, checksum: 222525ec7c94cbfdc35eba7b43525398 (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | 1. Introduction 1
1-1 Motivation……………………… 1 1-2 Organization…………………… 2 2. SRAM Architecture 3 2-1 Memory organization………… 3 2-2 Operation modes…………………5 2-2-1 Read operation……………… 5 2-2-2 Write operation…..…………7 2-3 Timing and power analysis……8 2-3-1 Memory timing parameters… 8 2-3-2 Power analysis in the simple SRAM…..….... 10 2-3-3 Delay analysis in the simple SRAM… ………. 11 2-4 Divided word line………………….……… …….. 13 2-4-1 Power consumption in the divided word line structure 14 2-4-2 Delay in the divided word line structure…..……….... 15 2-5 Memory circuits…………………….………………………..... 16 2-5-1 SRAM Cells……………………………...................... 16 2-5-2 Decoders…..………..................................................... 18 2-5-3 Column precharge circuits…........................................ 23 2-5-4 Sense amplifier............................................................. 25 2-5-5 Replica circuit............................................................... 25 2-6 Summary................................................................................. 28 3. Sense amplifier 29 3-1 Sense amplifier classification………………………………... 29 3-2 Delay analysis in voltage and current sense amplifiers……… 30 3-3 Conventional CMOS differential amplifier.............................. 32 3-4 Latch type sense amplifier………………………………........ 36 3-5 Current latched sense amplifier................................................ 38 3-6 The improved current latched sense amplifier......................... 40 3-7 Summary................................................................................... 43 4. A 4Kb SRAM circuit design 45 4-1 Introduction………………………………………….............. 45 4-2 Cell array…………….............................................................. 46 4-2-1 Divided Word Line…………………………….......... 46 4-2-2 Cell stability…..………............................................... 47 4-2-3 Layout…...................................................................... 48 4-3 Decoder………......................................................................... 49 4-4 Sense amplifier…………………………………………......... 51 4-5 4Kb SRAM simulation result................................................... 56 4-6 Conclusions.............................................................................. 59 5. Conclusions 61 6. References 63 | |
| dc.language.iso | en | |
| dc.subject | 記憶體 | zh_TW |
| dc.title | 以0.18um CMOS 積體電路技術設計250MHz 4Kb 靜態隨機存取記憶體 | zh_TW |
| dc.title | A 250MHz 4Kb SRAM Design in CMOS 0.18um Technology | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢,盧信嘉,丁達剛 | |
| dc.subject.keyword | 記憶體, | zh_TW |
| dc.subject.keyword | SRAM, | en |
| dc.relation.page | 64 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2005-07-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-94-1.pdf 未授權公開取用 | 2.67 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。