省電式晶片網路設計之計算機結構層共同合成演算法

Abstract

Network-on-Chip (NoC) 被視為解決未來單晶片系統 (SoC) 上日漸嚴重的連接線延遲問題，並提供高執行效能需求的一個可行的設計平臺。在本篇論文中，針對NoC為基礎的系統，我們提出了一個省電式合成演算法。這個演算法能在滿足時間限制條件下，同時考量硬體架構與軟體架構來達到使耗電量最少之目的。這裡指的硬體架構包括一個NoC的平臺以及一組含有不同類型的運算元件 (Processing Element)；軟體架構則包含工作 (Task) 如何分配到運算元件、運算元件與NoC平臺的幾何位置擺設，以及一個所有工作的靜態排程。我們的主要貢獻是：我們是第一個有系統地描述針對NoC平臺下軟、硬體共同設計的問題；並且，根據模擬冶鐵演算法 (Simulated Annealing)，我們提出了一個既有效率又有效果的省電式合成演算法來解決它。藉由我們所提出的架構，設計者可以同時探索硬體架構與軟體架構來找到一個符合時間限制且整體耗電量最少的軟硬體架構。

Network-on-Chip has been proposed as a practical development platform for future system-on-chip products to reduce interconnection delay and to boost a good performance. In this thesis, we propose an energy-aware algorithm which simultaneously synthesizes the hardware and software architectures of a NoC-based system to meet a performance constraint and minimize total energy cost. The hardware architecture of the synthesized systems consists of an NoC platform and a set of PE (Processing Element) of multiple types; the software architecture consists of allocation of tasks to PE, the topological mapping of PEs to the NoC architecture and a static schedule for the task set. As the main contribution, we first formulate the problem of architectural co-synthesis algorithm with HW/SW co-design for a heterogeneous NoC platform and then propose an effective and efficient SA-based algorithm to solve it. With the aid of this framework, the designer can explore both hardware and software architectures simultaneously to find a system-wise energy-minimal hardware configuration along with corresponding software architecture under tight performance constraints.