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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 顧孟愷 | |
| dc.contributor.author | Chien-Wei Ho | en |
| dc.contributor.author | 何建緯 | zh_TW |
| dc.date.accessioned | 2021-06-13T06:43:34Z | - |
| dc.date.available | 2008-08-16 | |
| dc.date.copyright | 2005-08-16 | |
| dc.date.issued | 2005 | |
| dc.date.submitted | 2005-07-29 | |
| dc.identifier.citation | REFERENCES (WORKS CITED, SELECTED BIBLIOGRAPHY)
[1] Erno Salminen, Vesa lahtinen, Kimmo Kuusilinna, Timo Hamalainen, “Overview of Bus-based System On Chip Interconnnections,” IEEE International Symposium on Circuits and System, vol. 2, pp. 372-375, May 2002 [2] Po-Hao Chang, “Hardware software co-design and Implementation of Wavelet-based Video Compression System,” Department of Electrical Engineering National Cheng Kung University, June 2002 [3] S. Hauck, “The roles of FPGAs in reprogrammable systems,” Proceedings of the IEEE, vol. 86, pp. 615-638, April 1998. [4] P Brunet, C Tanougast, and Y Berviller, “Hardware Partitioning Software for Dynamically Reconfigurable SoC Design,” Proceedings of the 3rd IEEE International Workshop, pp. 106-111, July 2003. [5] J. Harkin, T. M. McGinnity, and L. P. Maguire, “Partitioning methodology for dynamically reconfigurable embedded systems,” IEEE Proceedings - Computers and Digital Techniques, vol.147, pp. 391-396, November 2000. [6] Sitanshu Jain, “Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library,” Proceedings of IEEE international conference on VLSI design, pp. 400-405, Jan. 1998. [7] P Waldeck, and N Bergmann, “Dynamic Hardware-Software Partitioning on Reconfigurable System-on-Chip,” IEEE Proceedings - System-on-Chip for Real-Time Applications, pp. 102-105, July 2003. [8] Joao Canas Ferreira, and Jose Silva Matos, “Mixed Hardware/Software Applications on Dynamically Reconfigurable Hardware,” IEEE International Electronics, Circuits and Systems, vol. 1, pp. 97-100, Sept. 1998. [10] Nikil Dutt and Kiyoung Choi, “Configurable Processors for Embedded Computing”, vol. 36, no. 1, pp. 120-123, Jan. 2003. [11] AMBA specification, refer to ARM Limited web page: http://www.arm.com [12] Altera Excalibur Literature, http://www.altera.com/literature/lit-exc.jsp [13] Easy Configurable Operating System, http://sources.redhat.com/ecos [14] Booting Excalibur Devices, http://www.altera.com/literature/an/an187.pdf [15] Athanassios Skodras, Charilaos Christopoulos, and Touradj Ebrahimi, “The JPEG 2000 Still Image Compression Standard”, IEEE Signal Processing Magazine, no. 5, vol. 18, pp. 36-58, Sep. 2001. [16] Open JPEG2000 codec, http://www.tele.ucl.ac.be/PROJECTS/OPENJPEG/ [17] R. G. Gallager,“Low Density Parity Check Codes,” IRE Transactions on Information Theory, pp. 21-28, January 1962. [18] R. G. Gallager, Low Density Parity Check Codes, MIT Press, Cambridge, Mass., 1963. [19] Y. Kou, S. Lin and M. Fossorier, “Low Density Parity Check Codes based on Finite Geometries: A Rediscovery,” Proc. IEEE International Symposium on Information Theory, Sorrento, Italy, June 25-30, 2000. [20] B. Mei, P. Schaumont, and S. Vernalde, “A Hardware-Software Partitioning and Scheduling Algorithm for Dynamically Reconfigurable Embedded Systems,” In Proc. of ProRISC 2000, 2000. [21] Arato, P., Juhasz, S., Mann, Z.A., Orban, A., and Papp, D., “Hardware-software partitioning in embedded system design,” IEEE International Symposium on Intelligent Signal Processing, pp.197-202, Sept. 2003. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/35191 | - |
| dc.description.abstract | Nowadays when we want to do a design, we need to software-hardware partition first. It is because that we want to put some heavy loading parts of the design into hardware. That would improve the performance of the whole design. Generally if we can put as many functions into hardware as we can, we will get much performance improvement. So, besides the software-hardware partitioning consideration, we need to have a rapidly method to let the Compute Intensive Part (CIP) run in hardware. We propose a Dynamically Reconfigurable Hardware Library (DRHL) method. When we put the CIP into DRHL, we can change to use software Intellectual Property (IP) or hardware IP smoothly. So, we can easily test if our software IP and hardware IP have the same functionality. We also can enhance computation power in System-On-Chip (SOC) with FPGA blocks. Our method provides to reach a better trade-off among flexibility performance and power. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-13T06:43:34Z (GMT). No. of bitstreams: 1 ntu-94-R92922060-1.pdf: 723196 bytes, checksum: 81a8ee961b7083d486b49d285f814c56 (MD5) Previous issue date: 2005 | en |
| dc.description.tableofcontents | Chapter
1.INTRODUCTION 1 1.1 A review of Hardware/Software Codesign 1 1.2 Platform-based Design and IP Reuse 2 1.3 Introduction to dynamically reconfigurable hardware library 3 1.4 Thesis organization 4 2.RELATED WORK 5 3.USING DYNAMICALLY RECONFIGURABLE HARDWARE LIBRARY 7 3.1 The goal of dynamically reconfigurable hardware library 7 3.2 Hardware view of IP 7 3.2.1 Software device driver 9 3.2.2 Interface controller 10 3.2.3 Interface of each IP 12 3.3 Usage of the dynamically reconfigurable hardware library 13 3.3.1 “Search_addr” function 13 3.3.2 “config_logic” function 14 3.3.3 “ip_driver” function 15 3.4 Operation of dynamically reconfigurable hardware library 17 3.5 Add an IP’s effort 17 3.6 The flexibility gain with using this method 19 4.CASE STUDY 20 4.1 Altera ARM Excalibur Development Environments 20 4.2 Porting of real time operating system 23 4.3 Overview of each IP 28 4.3.1 Introduction to JPEG2000 28 4.3.2 AES encoder and DES encoder 31 4.3.2.1 Introduction of DES 31 4.3.2.2 Introduction to AES 33 4.3.3 Introduction to LDPC 36 4.4 Add DWT into DRHL 38 4.5 Experimental result 43 5.CONCLUSIONS AND FUTURE WORK 47 5.1 Conclusions 47 5.2 Future Work 47 REFERENCES 48 | |
| dc.language.iso | en | |
| dc.subject | 矽智財 | zh_TW |
| dc.subject | 現場可重定址陣列 | zh_TW |
| dc.subject | 系統晶片 | zh_TW |
| dc.subject | FPGA | en |
| dc.subject | IP | en |
| dc.subject | SOC | en |
| dc.title | Dynamically Reconfigurable Hardware Library based of FPGA | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 93-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳信樹,施吉昇,洪士灝,楊佳玲 | |
| dc.subject.keyword | 現場可重定址陣列,系統晶片,矽智財, | zh_TW |
| dc.subject.keyword | FPGA,SOC,IP, | en |
| dc.relation.page | 49 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2005-07-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
| 顯示於系所單位： | 資訊工程學系 | |
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